In this paper, silicon carbide-based analytical model for gate-stack dual metal nanowire field effect transistor (gate-stack DM NW FET) has been analyzed by solving the 2D Poisson's equation using parabolic approximation method for electric potential, subthreshold current and subthreshold slope. The results have been examined for various silicon carbide film depth and channel length. The results predicted by the analytical model have excellent agreement with simulated results obtained by ATLAS 3D device simulator. A gate-stack having high k-dielectric material, that is, Hafnium oxide (HfO 2 ) along with aluminum oxide (Al 2 O 3 ) has been used. Also, performance characteristics of gate-stack DM NW FET have been compared with the performance characteristics of nanowire field effect transistor (NW FET), Nanowire field effect transistor (NW FET) (Sic) and dual metal nanowire field effect transistor (DM NW FET) (SiC). It is so proved that our proposed device, that is, gate-stack DM NW FET (4H-SiC) exhibits superior performance in terms of drain current (I ds) , transconductance (g m ), output conductance (g d ) and cut off frequency (f T ) than the existing devices.

Rapidly growing technology has raised demands for fast and efficient real time digital signal processing applications. Multiplication is one of the primary arithmetic operations every application demands. A large number of multiplier designs have been developed to enhance their speed. Active research over decades has lead to the emergence of Vedic Multipliers as one of the fastest and low power multiplier over traditional array and booth multipliers. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. A large number of them have been proposed using Urdhava Tiryakbhyam sutra rendering them most efficient in terms of speed. The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of Image processing and Digital signal processing, particularly the different modifications of existing Vedic Multiplier architectures enhancing their speed and performance parameters.

This article presents an analytical study and effect of temperature (T = 100, 200, 300, 400 K) on various parameters of gate-stack dual metal nanowire field-effect transistor (gate-stack DM NW) FET (4H-SiC) and gate-stack dual metal nanowire field-effect transistor (gate-stack DM NW FET) (Si). The parabolic approximation is used to solve the 2D Poisson's equation for surface potential, electric field, drain current (I ds ), transconductance (g m ), output conductance (g d ), and analog performance is evaluated. Electron concentration, electron velocity, drain induced barrier lowering, DIBL, and noise figure (NF) have also been investigated for a fair comparison and shows that 4H-SiC based gate-stack DM NW FET device is more insensitive to temperature changes than the silicon-based gate-stack DM NW FET. Furthermore, gatestack DM NW FET (4H-SiC) has better electrical performance with temperature variation than gate-stack DM NW FET (Si). The simulations have been carried out using the ATLAS 3D device simulator. Analytical results are in close agreement with the simulated results.

In this paper, the authors have provided a brief review of the recent advances in the Shannon sampling theory. In particular, they discuss the work related to 1-D signal reconstruction involving the samples taken below the Nyquist rate using nonlinear/time-variant systems. The extensions of the sampling theorems to the fractional Fourier and Linear canonical transform domains are also discussed.

No abstract