Applications of vedic multiplier designs - A review

Abstract

Rapidly growing technology has raised demands for fast and efficient real time digital signal processing applications. Multiplication is one of the primary arithmetic operations every application demands. A large number of multiplier designs have been developed to enhance their speed. Active research over decades has lead to the emergence of Vedic Multipliers as one of the fastest and low power multiplier over traditional array and booth multipliers. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. A large number of them have been proposed using Urdhava Tiryakbhyam sutra rendering them most efficient in terms of speed. The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of Image processing and Digital signal processing, particularly the different modifications of existing Vedic Multiplier architectures enhancing their speed and performance parameters.

Analysis of Multiplication Based on Vedic Mathematics

“…This can be easily demonstrated by the following diagram as shown in Figure 1 [3][4][5][6][7][8][9]. The result obtained will be J6J5J5J4J3J2J1J0 Each component of J has its own formula to give the conclusion of particular multiplication [7][8][9][10][11][12]. The process of obtaining components of J is clearly explained in the following Figures 2.…”

“…The obtained result would be J4J3J2J1J0. As similar to the 4-bit multiplication these components of J also will have their formulas to reach the final destiny of multiplication [9][10][11][12][13][14]. The formulas used in the process are listed below.…”

“…In 2011, P. Saha et al have reported efficient circuit for factorial calculation of number by using iterative multiplication based on the Vedic mathematics sutras "Urdhva Tiryagbhyam" and "Nikhilam" [9][10]. In this paper author suggested ASIC design for factorial calculation of number [9,11].…”

“…It is the third sutra of the Vedic mathematics. In this method the carry from the previous step is added and the digits from the both sides of the lines are multiplied [9][10][11][12][13][14].…”

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

“…A re-configurable FIR filter has been suggested using CSD. 4 Various multipliers, and adders 5 were used, and a comparison was drawn to reduce hardware cost, i.e., area utilization. We extensively studied the performance of the FIR filter for various computational (multipliers and adders) elements for the transposed FIR filter structure.…”