A scalable SIMD/MIMD mixed-mode parallel processor architecture called XC core is proposed to meet the high and diverse performance requirements of embedded multimedia applications. XC core supports both the SIMD and MIMD computing models at low hardware cost by dynamically reconfiguring itself into datapath circuits or control circuits, i.e., trading off between performance and flexibility. A control processor is used to broadcast instructions to a whole SIMD PE (Processing Element) array or to a part of it while assigning a separate program to each PU (Processing Unit), that is mainly composed of the hardware resources of several PEs. RTL synthesis results show that area overhead for reconfiguration is merely 10% of the total area. Benchmark results show that the SIMD mode is effectively achieving high performance towards the regular and massive data parallelism portions of applications, while the MIMD mode enables acceleration of the remaining part of applications whose implementation using a pure highly parallel SIMD architecture would otherwise be impossible. The results show that the XC core design is competitive against more complex processors, with respect to both its cost efficiency as a highly parallel SIMD processor and its flexibility as a multicore MIMD processor, against a wide range of applications.

We have developed an "XC core" processor that achieves low cost, high performance, and low power consumption through the use of a highly parallel SIMD architecture (the SIMD mode), as well as achieves high flexibility by morphing into a MIMD architecture (MIMD mode). In this paper, we evaluate the effectiveness of the MIMD mode by using a white line detection algorithm for open roads. Our evaluation shows that the algorithm can be processed in real time (less than 33 ms) by using the MIMD mode to execute verification of white line segments, which is a part of the algorithm not suitable to be executed by the SIMD mode. We also show that the verification can be executed five times faster by using region of interest (ROI) transfer instructions to efficiently transfer the ROI of an image. Furthermore, we also measured the execution time in the MIMD mode with changing the number of processing units (PUs) used, from 2 to 4, 8, 16 and 32. The measured results show that the performance improvement rate slows down when using more than 16 PUs in the MIMD mode, mainly due to insufficient parallelism in the verification process. Overall, a 10.68 times speedup was achieved by using 32 PUs in the MIMD mode, compared with only using the SIMD mode.

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