A low-cost mixed-mode parallel processor architecture for embedded systems

Abstract

A scalable SIMD/MIMD mixed-mode parallel processor architecture called XC core is proposed to meet the high and diverse performance requirements of embedded multimedia applications. XC core supports both the SIMD and MIMD computing models at low hardware cost by dynamically reconfiguring itself into datapath circuits or control circuits, i.e., trading off between performance and flexibility. A control processor is used to broadcast instructions to a whole SIMD PE (Processing Element) array or to a part of it while assigning a separate program to each PU (Processing Unit), that is mainly composed of the hardware resources of several PEs. RTL synthesis results show that area overhead for reconfiguration is merely 10% of the total area. Benchmark results show that the SIMD mode is effectively achieving high performance towards the regular and massive data parallelism portions of applications, while the MIMD mode enables acceleration of the remaining part of applications whose implementation using a pure highly parallel SIMD architecture would otherwise be impossible. The results show that the XC core design is competitive against more complex processors, with respect to both its cost efficiency as a highly parallel SIMD processor and its flexibility as a multicore MIMD processor, against a wide range of applications.

Performance Evaluation of a Dynamically Switchable SIMD/MIMD Processor by Using an Image Recognition Application

“…By reusing the hardware of four PEs in these ways, the additional hardware costs for implementing the MIMD mode, including the costs for the ROI transfer instructions described in Section 2.2, have been kept to approximately 10% of the costs for the whole XC core 6) .…”

“…To solve these issues, we have designed a processor architecture called the XC core, which can dynamically switch between the SIMD and MIMD modes 6) . In addition to the conventional SIMD mode, the XC core also implements a MIMD mode in which four PEs are reconfigured as one operation unit (PU: Processing Unit), as shown in Fig.…”

IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements

“…Such direction of evolution will enhance the versatility of vision processors, however, the strict cost limitation coming from the product side and the performance and flexibility requirements coming from the vision application side will drive such research activities, whereby the architectural design approaches for vision processors will be differentiated from those for more general-purpose oriented future multi-or many-core processor design approaches. One research activity toward this challenge can be found in [8], where a novel hardware component reuse design methodology is proposed to support task level parallelism through low-cost dynamic reconfiguration of a pure highly parallel SIMD architecture.…”