Abstract:In this paper divide by N prescaler counter is discuss. Instead of using conventional counter design technologies, a decision logic circuit is needed to generate predictable counting states. This circuit can be design by using transmission gate logic as a basic design cell. An initial module generates predictable counting states for higher significant bit modules through the state look-ahead path. In order to attain high operating frequency a high speed parallel counter is presented. In our work the counter operating frequency is varied by using a parallel counter architecture of transmission gate base flip-flops. The operation speed is improved by reduction of the critical path delay and the low power consumption can be achieved due to less number of interconnects. Simulation results in a standard 50nm CMOS process.

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This paper we mainly emphasize on simulation & synthesis of microstrip line by using powerful simulation tools like sonnet and matlab. Many researchers have investigated the dispersion characteristics of microstrip lines at different higher frequency range. This paper we analyzed the microstrip line with characteristic impedance 50Ω at frequency range 1 to 20GHz for Alumina, Gallium Arsenide and Silicon substrate materials. All parameters of the microstrip lines are exactly determined from the empirical formula of microstrip line. Here we compare the results of the dispersion formulas on the software tools.