Energy harvesting technology is regarded as a feasible solution for the continuous power supply of microelectronic devices. Efforts have been made to improve the output power of all kinds of energy harvesting devices. This paper reports a 2 × 2 array piezoelectric–electromagnetic hybrid energy harvester that achieves high power output through the combination of piezoelectric and electromagnetic conversion. The harvester included four piezoelectric–electromagnetic hybrid modules, each of which consisted of a piezoelectric sheet, a permanent magnet and a wound coil. The permanent magnet, also serving as the mass block of the cantilever beam when subjected to external stimulus, contributed to a large displacement of the vibration and generated high output power. At an acceleration of 1 g and a resonance frequency of 70.4 Hz, the measured maximum output power of the hybrid energy harvester was 66.08 mW, of which the piezoelectric and electromagnetic portions were 56.96 and 9.12 mW, respectively. Furthermore, in a charging experiment, a capacitor of 23.5 mF was charged to 11.5 V within 20 s, which demonstrates a practical application of the hybrid energy harvester for microelectronic devices.

A novel photodiode array structure is proposed and implemented in the paper. Based on the SOI substrate, the structure adopts double SiO2 layers for isolation among PN junctions. Compared with incumbent photodiode arrays with a single isolation layer, the novel design shows less leakage current, less noise, high optical response sensitivity, and better compatible integration with other devices. The dark current of this structure is less than nanoamperes (10-9 A), with the benefits of 1000 times’ less leakage current than that of other structures, and a higher sensitivity with a response speed less than 200 ns. The device is fabricated and characterized. The doping concentration and structural profile are characterized. The fabricated device is packaged with a photo LED and the MOS device to act as the MOS relay driver. The wavelength used in the photodiode is between 500 nm-560 nm, with peak wavelength 520 nm, which can be used to drive MOS device.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

In order to achieve high resolution in Successive Approximation Register (SAR) Analog to Digital Converter (ADC), a novel noncoupling capacitor split capacitor array structure is proposed, which solves the coupling capacitor mismatch problem in the traditional split capacitor array structure. This paper analyzes the structure and its capacitor array mismatch. Based on the structure and analysis, a 12-bit SAR ADC is designed and implemented in GSMC 0.11 [Formula: see text]m CMOS process. The measured results show that the Signal to Noise Ratio (SNR) is 72.61 dB and Effective Number Of Bits (ENOB) is 11.77 bit, which prove the advantages of this structure in the design of high resolution SAR ADC.