The COM2 SiGe modular BiCMOS technology has been developed to allow efficient design and manufacturing of digital, mixed-signal, and RF integrated circuits, as well as enabling system-on-chip (SOC) integration. The technology is based on the 0.16pm COM2 digital CMOS process which features 1.5V NMOS and PMOS transistors with 2.4nm gate oxide, 0.135pm gate length, and up to 7 metal levels. Technology enhancement modules including dense SRAM, SiGe NPN bipolar transistor, and a variety of passive components have been developed to allow the COM2 technology to be cost-effectively optimized for a wide range of applications.

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In small form factor (SFF) platforms, motherboard space, and power are some of the most critical factors for their design. System memory bus is one of the major contributors to the I/O power consumption. Historically, the memory bus has always been terminated on the motherboard at the receiver end to meet SI/timing requirements. But these terminations result in significant power dissipation. This paper investigates the impact of removing these terminations [No-ODT (On Die Termination) for Data/Strobe and No-RttParallel termination for Command/Control (CMD/CNTL) for different memory configurations], and provides motherboard routing recommendations to support No-ODT/No-Rtt without violating SI/timing specs. This paper also highlights the savings in power and motherboard space achieved by removing these terminations.

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