No abstract

In the last decade the amount of digital data generated in connection with digital devices such as cameras, media players and high-definition TVs has seen a significant growth. This requires tuners for home networking such as MoCA with increasingly large bandwidth. Though advanced CMOS technology allows for the design of high-speed circuits and systems that can meet the need for more bandwidth, 40nm feature sizes and beyond introduce new challenges in analog circuit design [1]. Moreover, dependence on environmental conditions of device spread and matching performance with parasitic coupling can drastically reduce the overall system performance.The integration of analog/RF circuits with the digital part in an SoC enables the use of inexpensive DSP power to calibrate non-idealities. Digitally-assisted RF allows for more power-and area-efficient systems that achieve good performance over process, temperature and supply (PVT) variations. This paper presents a calibration scheme that uses the available DSP power to perform the transmitter image, local oscillator feed-through (LOFT) and output power calibration by sub-sampling the transmitter spectrum. The system achieves an IR of 55dBc, a 40dBc LOFT and a ±0.6dB gain accuracy up to a 1.6GHz LO frequency.OFDM signals require an accurate control of LOFT, image level and delivered output power to meet the required performance. Though LOFT does not harm signal reception, a high LOFT level results in transmission of redundant energy and it reduces the receiver's dynamic range. A high image level due to I/Q imbalances affects the reception of the signal, degrading the receiver SNR. Finally, an accurate control of the transmitter output power removes the need for sophisticated power estimation procedures, reducing the system complexity.Transmitter LOFT or I/Q calibration can be performed at factory level [2] at the expense of a higher production cost or by dedicated mixed-signal circuitry [3,4] at the expense of extra chip area. The proposed calibration scheme reuses part of the receiver (the ADC) to perform all the calibration steps, minimizing chip area and production cost. Figure 24.1.1 shows the transmitter block diagram including the calibration path.The transmitter signal path consists of an I/Q baseband filter with a 1dB bandwidth tunable between 22MHz and 200MHz, a highly linear single-sideband mixer and a PA driver (PAD). The local oscillator (LO), used to up-convert the baseband signal, covers the frequencies between 50MHz and 1.6GHz.During calibration, either the upconversion mixer output (I/Q and LOFT calibration) or the PAD output (TX gain calibration) are looped-back to the RX ADC. A variable bandwidth buffer (VBB) is used to drive the RX ADC input and it is the only extra block required in the proposed calibration. The 12b ADC is clocked by an integer-N PLL driven by a 50MHz crystal-based reference signal. In the current prototype, CML buffers are used to drive the ADC outputs off-chip for data analysis. During calibration, a test tone (f BB ) is generated in ...

No abstract

This paper analyses the typical digital modulation techniques used in today's wireless communications. The paper presents the characteristics of the modulation techniques and determines the figure of merit for each particular modulation: Bit Error Rate (BER) vs. Signal-toNoise Ration (SNR). The analysis emphasizes the importance ofsuch figure ofmerit in the context ofSoftware Defined Radios (SDR).

No abstract