A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3&lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$ {&amp;lt;} {-}$&lt;/tex&gt;&lt;/formula&gt;58 dBc in 40 nm CMOS

Spiridon, Silvian; Tang, J. van der; Yan, Han; Chen, Huafeng; Guermandi, Davide; Liu, Xiaodong; Arslan, E.; Goes, Frank van der; Bult, Klaas

doi:10.1109/jssc.2013.2253219

Cited by 26 publications

(13 citation statements)

References 7 publications

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“…Lastly, an IR drop along the DAC supply lines causes a variation in the gate-to source voltage of the current source leading to DNL errors in the DAC [16]. Similarly, an IR drop in the switch driver supply results in timing errors in the DAC switches [21]. In summary, as the number of cells (N ) increases, it becomes increasingly difficult to maintain the same DAC performance.…”

Section: Characteristics Of Nyquist Dacsmentioning

confidence: 99%

“…A survey of the published literature shows that DACs for wireline applications such as cable modems or backplanes require a high output swing e.g 1.6 V reported in [48] and 2.5 V in [16] [21]. On the other hand, DACs for wireless applications that connect to an upconversion mixer require relatively a lower swing e.g.…”

Section: Dac Current Cell Designmentioning

confidence: 99%

“…In many communication applications with multiple carriers e.g. OFDM, the IM3 can be a more important specification than HD3 [16,21]. To measure the IM3, two tones of equal input amplitude (typically half the full scale voltage available or −6 dBFS) are used.…”

Section: Dac Current Cell Designmentioning

confidence: 99%

“…CMOS switch drivers have been shown to have the steepest transitions [16,50]. Figure 2-34 shows a such a fast switching driver used for a 5 GHz speed in 40-nm CMOS [21]. However, for the two timeinterleaved DACs in this dissertation, this latch based switch driver cannot be used as multiplexing of two channels using a half-rate-clock is also involved.…”

Section: Switch Driver Designmentioning

confidence: 99%

“…The traditional method of DAC testing includes the use of a high-speed receiver IO interface on the digital inputs [21,60]. The high-speed interface can directly transfer data at the full rate [60] or use multiple lower frequency streams that are serialized on-chip [21].…”

Section: Dac Testing Challengesmentioning

confidence: 99%

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Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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Digital-to-analog (D/A) converters (or DACs) are one the fundamental building blocks of wireless transmitters. In order to support the increasing demand for high-data-rate communication, a large bandwidth is required from the DAC. With the advances in CMOS scaling, there is an increasing trend of moving a large part of the transceiver functionality to the digital domain in order to reduce the analog complexity and allow easy reconfiguration for multiple radio standards. ∆Σ DACs can fit very well into this trend of digital architectures as they contain a large digital signal processing component and offer two advantages over the traditionally used Nyquist DACs. Firstly, the number of DAC unit current cells is reduced which relaxes their matching and output impedance requirements and secondly, the reconstruction filter order is reduced.Achieving a large bandwidth from ∆Σ DACs requires a very high operating frequency of many-GHz from the digital blocks due to the oversampling involved. This can be very challenging to achieve using conventional ∆Σ DAC architectures, even in nanometer CMOS processes. Time-interleaved ∆Σ (TIDSM) DACs have the potential of improving the bandwidth and sampling rate by relaxing the speed of the individual channels. However, they have received only some attention over the past decade and very few previous works been reported on this topic. Hence, the aim of this dissertation is to investigate architectural and circuit techniques that can further enhance the bandwidth and sampling rate of TIDSM DACs.The first work is an 8-GS/s interleaved ∆Σ DAC prototype IC with 200-MHz bandwidth implemented in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. Two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate i.e. 4 GHz. This is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results from the prototype show that the DAC achieves 200-MHz bandwidth, −57-dBc IM3 and 26-dB SNDR, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows good potential for use in the transmitter baseband. While a good linearity is obtained from this DAC, the SNDR is found to iv be limited by the testing setup for sending high-speed digital data into the prototype.The performance of a two-channel interleaved ∆Σ DAC is found to be very sensitive to the duty-cycle of the half-rate clock. The second work analyzes this effect mathematically and presents a new closed-form expression for the SNDR loss of two-channel DACs due to the duty cycle error (DCE) for a noise transfer function (NTF) of (1 − z −1 ) n . It is shown that a low-order FIR filter after the modulator helps to mitigate this problem. A closed-form expression for the SNDR loss in the presence of this filter is also developed. The...

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Section: Characteristics Of Nyquist Dacsmentioning

confidence: 99%

Section: Dac Current Cell Designmentioning

confidence: 99%

Section: Dac Current Cell Designmentioning

confidence: 99%

Section: Switch Driver Designmentioning

confidence: 99%

Section: Dac Testing Challengesmentioning

confidence: 99%

See 3 more Smart Citations

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Bhide

2015

Linköping Studies in Science and Technology. Dissertations

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A high power fully integrated single‐chip CMOS transmitter for wireless communication of unmanned aircraft system

Roy

Dawn

2016

Micro & Optical Tech Letters

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This letter presents a high power fully integrated single‐chip CMOS transmitter for automatic dependent surveillance‐broadcast (ADS‐B) of unmanned aircraft system (UAS), operating at both 978 MHz Universal Access Transceiver (UAT) mode and 1090 MHz Extended Squitter (1090 ES) mode. The 4.38 mm × 0.95 mm fully‐integrated transmitter chip fabricated using 0.18 um CMOS process exhibits modulated output power of 23 dBm at 978 MHz with 102 MHz bandwidth, showing a potential replacement of the state‐of‐the‐art technology by significantly reducing the size and overall cost of the complete ADS‐B system. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:432–439, 2017

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Toward 5G Software Defined Radio Receiver Front-Ends

Spiridon¹

2016

SpringerBriefs in Electrical and Computer Engineering

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A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3<formula formulatype="inline"> <tex Notation="TeX">$ {<} {-}$</tex></formula>58 dBc in 40 nm CMOS

Cited by 26 publications

References 7 publications

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

Design of High-Speed Time-Interleaved Delta-Sigma D/A Converters

A high power fully integrated single‐chip CMOS transmitter for wireless communication of unmanned aircraft system

Toward 5G Software Defined Radio Receiver Front-Ends

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