In this work, we present a novel non-volatile spin transfer torque (STT) assisted spin-orbit torque (SOT) based ternary content addressable memory (TCAM) with 5 transistors and 2 magnetic tunnel junctions (MTJs). We perform a comprehensive study of the proposed design from the device-level to application-level. At the device-level, various write characteristics such as write error rate, time, and current have been obtained using micromagnetic simulations. The array-level search and write performance have been evaluated based on SPICE circuit simulations with layout extracted parasitics for bitcells while also accounting for the impact of interconnect parasitics at the 7nm technology node. A search error rate of 3.9x10 -11 is projected for exact search while accounting for various sources of variation in the design. In addition, the resolution of the search operation is quantified under various scenarios to understand the achievable quality of the approximate search operations. Application-level performance and accuracy of the proposed design have been evaluated and benchmarked against other state-of-the-art CAM designs in the context of a CAM-based recommendation system.

This article proposes a novel magnetoelectric (ME) effect-based ternary content addressable memory (TCAM). The potential array-level write and search performances of the proposed ME-TCAM are studied using experimentally calibrated compact physical models and SPICE simulations. The voltage-controlled operation of the ME devices eliminates the large joule heating present in the current-controlled magnetic devices and their low-voltage write operation makes them more energy-efficient compared to static random access memory-based TCAMs (SRAM-TCAMs). The proposed compact TCAM outperforms its SRAM counterpart with 1.35× and 14.4× improvements in search and write energy, respectively, and its nonvolatility eliminates the standby leakage. We project an error rate below 10 −4 while considering various sources of variation in magnetic and CMOS devices. At the application level, using memory-augmented neural networks (MANNs), we project a 2× energy-delay-area-product (EDAP) improvement over an SRAM-TCAM. 12 13 14 INDEX TERMS BiFeO 3 (BFO), magnetoelectric (ME), ME-magnetic random access memory (MRAM), memory-augmented neural network (MANN), micromagnetic, multiferroic, ternary content addressable memory (TCAM).I. INTRODUCTION 15 W ITH the ever growing limits imposed by intercon-16 nects, novel computing paradigms that may reduce 17 data traffic between logic and memory have become more 18 attractive. Various in-memory computing approaches [1] 19 are therefore being explored in the context of different 20 applications/domains such as neural networks [2], associative 21 memories [3], spin-torque nano-oscillators [4], probabilistic 22 computing [5], and reservoir computing [6]. Ternary content 23 addressable memory (TCAM) is an associative memory that 24 performs parallel data searches over a memory array and 25 outputs if/where a match occurs. TCAMs have been used 26 in a variety of applications, such as few-shot learning [7], 27 [8], deoxyribonucleic acid (DNA) read alignment [9], 28 deep random forest [10], and hyperdimensional comput-29 131 proper choice of device parameters, this would happen only 132 when there is a mismatch between the stored and search data. 133 If the search bit is ''X,'' then SL and SL are grounded, 134 which prevents T3 from discharging ML. If the stored bit 135 is ''X,'' then both MTJs are in the anti-parallel state and 136 V fix∼V s/2 . We use appropriate threshold voltages to ensure 137 that V s /2 is adequately lower than the threshold voltage of 138 T3 to prevent T3 from discharging ML. Table 2 summarizes 139 the search operation for all possible stored and search bits 140 combinations. It should be noted that kV s < V s /2, where 141 k ≡ R p /(R p + R ap ) (R p and R ap are the resistances of the 142 MTJs in the parallel and anti-parallel state, respectively).143Hence, the worst case in terms of the margins and the leakage 144 current in T3 is when a ''don't care'' bit is stored. V s values 145 and MTJ device parameters are discussed later in Section IV.

A diverse set of novel materials, physical phenomena, logic/memory devices, and circuit/system options/concepts are being pursued globally to design and develop the next generations of information storage and processing platforms. Many of these potential options are vastly different compared to their conventional counterparts and cannot be used as drop-in replacements. This research should therefore include several levels of abstraction, and must take a holistic approach to truly leverage the benefits offered by the promising options. Among the emerging materials and devices, magnetic and multiferroic devices are of particular interest thanks to their non-volatility, density, energy efficiency and durability. This paper presents a co-design framework for magnetic materials, devices, and memory arrays based on a hierarchy of physical models. Two major categories of devices are considered: spin-orbit-torque (SOT) and magnetoelectric (ME) random access memories. Circuit compatible experimentally validated/calibrated physical models for such devices is presented and used to optimize material and device parameters to minimize energy/delay for read and write operations for various target error rates. Finally, novel SOT and ME based cell designs for ternary content-addressable memories (TCAM) are presented and their potential performance is quantified against their SRAM and FeFET based designs using a comprehensive modeling and benchmarking framework.