Abstract. This paper presents a new CMOS buffer circuit topology for radiofrequency (RF) applications based on a fully-differential voltage-combiner circuit, capable of operating at low-voltage. The proposed circuit uses a combination of common-source (CS) and common-drain (CD) devices. The simulation results show good levels of linearity and bandwidth. To improve total harmonic distortion (THD) a source degeneration technique is used. The proposed circuit has been designed in a 130nm logic CMOS technology and it achieves a simulated gain of 1.54 dB, a bandwidth of 1.14 GHz for a total power dissipation of 13.34 mW, when driving an RF active probe (with 0.8 pF in parallel with 200 kΩ).

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Abstract. This paper describes and tries to demystify the use of different lowvoltage operation devices, such as dynamic threshold MOS transistors (DTMOS) with feedback techniques such as regulated-feedforward (RFF) and self-biasing (SB). Traditionally, DTMOS devices are only used when nominal supply voltages below 0.7 V are envisaged. Moreover, RFF and SB techniques are normally avoided since engineers designing high-performance amplifiers are afraid of additional stability concerns. This work demonstrates, through exhaustive simulation results over process, temperature and supply (PVT) corners using a standard 130 nm 1.2 V CMOS technology that, employing DTMOS in some specific devices can improve some performance parameters such as the open-loop low-frequency gain and, simultaneously, reduce significantly the variability over PVT corners. Moreover, it is also demonstrated that, there is no risk of operating at supply voltages higher than 1.2 V. Combining DTMOS with RFF and SB allows achieving reasonable gainbandwidth products (GBW) even operating at low-voltage (down to 0.7 V), together averaged power savings of the order of 8% and highly simplifies the design of the circuit (since no biasing circuitry is required).

In this paper a four-stage self-biased voltagecontrolled oscillator (VCO) is presented. The proposed ringoscillator circuit employs a combination of dynamic-threshold-MOS (DT-MOS) and bulk-driven transistors to design lowvoltage low-power VCO with high oscillation frequency. By using an auxiliary body-driven latch, the VCO achieves a wide operating frequency range from 0.88 to 1.36 GHz (more than 40% tuning range). Simulation results in a 65-nm CMOS technology shows frequency variations of 3% against temperature variation of -20 ºC to 85 ºC, with only 0.36 mW power consumption using a 0.7 V supply voltage.

In this paper, a new current-mode VCO-based delta-sigma modulator is presented to avoid the need to use operational-transconductance amplifiers (OTAs), which are usually the most power hungry building-blocks. The proposed hybrid structure doesn't require an explicit high-gain block in the loop filter in order to achieve high resolution with second order noise shaping. Simulation results show the proposed current-mode VCO-based ADC performance is able to achieve to SNDR/SNR of 85/85.4dB with 5MHz bandwidth with only 2dB gain in the front-end current-mode integrator. The circuit architecture uses two 4-bit pseudo-differential VCO-based quantizers, operating in parallel, and two current-steering DACs providing intrinsic dynamic element matching (DEM). Keywords-VCO-based; delta-sigma analog to digital converter (∆Σ-ADC); quantizer