A novel circuit sizing technique with improved accuracy and efficiency is proposed to resolve the sizing issues in the analog circuit design. The grey wolf optimization (GWO) algorithm has the total number of iterations divided equally for exploration and exploitation, overlooking the impact of balance between these two phases, aimed for the convergence at a globally optimal solution. An enhanced version of a typical GWO algorithm termed as enhanced grey wolf optimization (EGWO) algorithm is presented with improved exploration ability and is successfully applied in analog circuit design. A set of 23 classical benchmark functions is evaluated and the outcomes are compared with recent state of the art. A conventional two-stage CMOS operational amplifier circuit realized in UMC 180nm CMOS technology is used as a benchmark to validate the efficiency and accuracy of the proposed optimization technique. A statistical study is also conducted over the final solution to investigate the exploration ability of the algorithm proving it to be one of the robust and reliable techniques.

Abstract:With the scaling of transistor feature size and increased integration density, power density has increased, resulting in high chip temperature, thus degrading the performance and lifetime of the chip. In this work, an ultralow power smart temperature sensor employing a frequency locked loop technique is developed in 65 nm standard CMOS process. The circuit works on the principle of voltage to frequency conversion, exploiting the thermal dependency of threshold voltage (V th ) of MOS transistors in the subthreshold region. The sensor along with signal conditioning subcircuits has a low power consumption of 1.92 µ W, while operating over -55• C to +125• C with a conversion rate of 10K samples/s. The output frequency corresponding to temperature has its temperature coefficient insensitive to process variation and therefore requires one-point calibration. Due to the simple signal conditioning circuitry, the sensor consumes an estimated area of 0.003 mm 2 . Since the sensor has all its subcircuits working in the subthreshold region, it is suitable for low power applications.

Purpose This paper aims to resolve the sizing issues of analog circuit design by using proposed metaheuristic optimization algorithm. Design/methodology/approach The hybridization of whale optimization algorithm and modified gray wolf optimization (WOA-mGWO) algorithm is proposed, and the same is applied for the automated design of analog circuits. Findings The proposed hybrid WOA-mGWO algorithm demonstrates better performance in terms of convergence rates and average fitness of the function after testing it with 23 classical benchmark functions. Moreover, a rigorous performance evaluation is done with 20 independent runs using Wilcoxon rank-sum test. Practical implications For evaluating the performance of the proposed algorithm, a conventional two-stage operational amplifier is considered. The aspect ratios calculated by simulating the algorithm in MATLAB are later used to design the operational amplifier in Cadence environment using 180nm CMOS standard process. Originality/value The hybrid WOA-mGWO algorithm is tailored to improve the exploration ability of the algorithm by combining the abilities of two metaheristic algorithms, i.e. whale optimization algorithm and modified gray wolf optimization algorithm. To build further credence and to prove its profound existence in the latest state of the art, a statistical study is also conducted over 20 independent runs, for the robustness of the proposed algorithm, resulting in best, mean and worst solutions for analog IC sizing problem. A comparison of the best solution with other significant sizing tools proving the efficiency of hybrid WOA-mGWO algorithm is also provided. Montecarlo simulation and corner analysis are also performed to validate the endurance of the design.

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