In this contribution we present a novel general model for adaptive processors. We describe its basic principle of operation and introduce several formal characterizations. The adaptive operations that are possible with this model are thoroughly discussed. The model allows runtime variations of the type and number of functional units as well as variations of the communication structure. We introduce simple heuristics to achieve adaptivity of the architecture. Experimental results show that a processor implementing this model can adapt its architecture to the requirements of diverse applications.

Dynamically reconfigurable architectures offer the opportunity to migrate software into hardware functional units at runtime. Architectures derived from the AMI-DAR model exhibit such possibilities. Yet, the question has to be answered, which parts of the running application should be transformed into hardware. The migration of complete methods or procedures into hardware is often not feasible. In this contribution we show a hardware circuit that enables the processor to collect an execution profile of Java methods with a high resolution. We also show, how this profile information can be used to make reasonable choices for candidate instruction sequences.

Reconfigurable devices like Configurable Systems on a Chip (CSoCs) have the ability to exchange parts of hardware during runtime. Multimedia applications often require computing power and often can be accelerated by specific hardware circuits. In this contribution we present the effect of hardware acceleration in reconfigurable devices. We introduce a new model of adaptive processors and describe its basic principle of operation. The model allows runtime variations of the type and number of functional units (including application specific FUs) as well as variations of the communication structure. Then, we discuss our multimedia kernel Inverse Discrete Cosine Transformation (IDCT) and the ability of shifting different parts of the IDCT into hardware. Simulation results show that hardware acceleration of multimedia operations in an adaptive processor leads to significant performance gains and therefore reduces energy consumption.

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