The Organic Features of the AMIDAR Class of Processors

Gatzka, Stephan; Hochberger, Christian

doi:10.1007/978-3-540-31967-2_11

Cited by 4 publications

(4 citation statements)

References 8 publications

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“…Therefore, we designed a set of several adaptive operations that may be applied to it. In [2], we have shown how to identify the conflicting bus taps and we have also shown a heuristic to modify the bus structure to minimize the conflicts. In order to exchange data between two functional units, both units have to be connected to the same bus structure.…”

Section: Adaptive Communication Structuresmentioning

confidence: 99%

“…The token set consists of three parts: (1) the tokens that transport input data to the SFU, these tokens are sent to the appropriate data sources (e.g., object heap), (2) the tokens that control the operation of the SFU, that is, that start the operation (which happens once the input data is available) and emit the results, and (3) the token set that stores the results of the SFU operation in the corresponding memory.…”

Section: Functional Unit Integrationmentioning

confidence: 99%

“…In order to prove the capabilities of our model, we have implemented a cycle accurate simulator, which allows the analysis of individual aspects regardless of the underlying technology. In previous papers, we have already discussed the effects of bus-level adaptivity and evolution of functional units [2].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

Döbrich¹,

Hochberger²

2011

International Journal of Reconfigurable Computing

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The design of energy-efficient systems has become a major challenge for engineers over the last decade. One way to save energy is to spread out computations in space rather than in time (as traditional processors do). Unfortunately, this requires to design specialized hardware for each application. Also, the nonrecurring expenses for the manufacturing of chips continuously grow. Implementing the computations on FPGAs and CGRAs solves this dilemma, as the non recurring expenses are shared between many different applications. We believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures as no expert knowledge of synthesis and technologies is required. In this paper, we give a detailed analysis of the amount and specialization of resources in a CGRA that are required to grant a significant speedup of Java bytecode. In fact, we show that even a relatively small number of specialized reconfigurable resources is sufficient to speed up applications considerably. Particularly, we look at the number of dedicated multipliers and dividers. Also, we discuss the required number of concurrent memory access operations inside the CGRA. Again, it shows that two concurrent memory access operations are sufficient for almost all applications.

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Section: Adaptive Communication Structuresmentioning

confidence: 99%

Section: Functional Unit Integrationmentioning

confidence: 99%

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Exploring Online Synthesis for CGRAs with Specialized Operator Sets

Döbrich¹,

Hochberger²

2011

International Journal of Reconfigurable Computing

Self Cite

View full text Add to dashboard Cite

show abstract

“…In [27], we have shown how to identify the conflicting bus taps and we have also shown a heuristics to modify the bus structure to minimize the conflicts.…”

Section: Adaptive Communication Structuresmentioning

confidence: 99%

Low-Complexity Online Synthesis for AMIDAR Processors

Döbrich¹,

Hochberger²

2010

International Journal of Reconfigurable Computing

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Future chip technologies will change the way we deal with hardware design. First of all, logic resources will be available in vast amount. Furthermore, engineering specialized designs for particular applications will no longer be the general approach as the nonrecurring expenses will grow tremendously. Reconfigurable logic has often been promoted as a solution to these problems. Today, it can be found in two varieties: field programmable gate arrays or coarse-grained reconfigurable arrays. Using this type of technology typically requires a lot of expert knowledge, which is not sufficiently available. Thus, we believe that online synthesis that takes place during the execution of an application is one way to broaden the applicability of reconfigurable architectures. In this paper, we show that even a relative simplistic synthesis approach with low computational complexity can have a strong impact on the performance of compute intensive applications.

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Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors

Hochberger

Jung

Engel

et al. 2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

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Abstract-The large expense of current chip fabrication can generally only be amortized for large manufacturing volumes. Thus, it is desirable to build adaptable chips that can be customized to the application needs after production. In this contribution we show that this adaptation is possible even without reconfigurable HW components. We propose synthilation, a new method for adapting the processor to the application requirements. It combines methods of hardware synthesis and software compilation to map high-level descriptions to hardware components of the processor. Our approach is applicable to varying degrees of reconfigurability, reaching from static microarchitectures just with writable control stores (variable microcode), to the exploitation of instruction level parallelism with multiple computational units. We consider both a practical real-world example as well as theoretical bounds on the speed-ups achievable by our method.

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The Organic Features of the AMIDAR Class of Processors

Cited by 4 publications

References 8 publications

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

Exploring Online Synthesis for CGRAs with Specialized Operator Sets

Low-Complexity Online Synthesis for AMIDAR Processors

Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors

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