Design teams have embraced hardware verification accelerators that enable pre-silicon firmware development. However, emulation is inapplicable for large mixed signal designs. We introduce a methodology that allows for the reuse of analog behavioral models in verification accelerators. We provide a set of pragmas that allow real number models to be converted to fixed point and synthesized and introduce an approach for demonstrating the correctness of these models. We demonstrated this by emulating a large cellular modem within 3,000× the speed of real life, a 3,000,000× speedup over analog simulations, and a 120× speedup over RTL simulations.