Over the past year two distinct answers have emerged regarding SoC design methodologies. On the one hand, it is posited in the Reuse Methodology Manual, that a logic synthesis-based design methodology can be used effectively to develop system chips. An alternative methodology focuses on integration (or "reference") platforms and the customization of the basic application-specific platform through the addition of selected SW and/or HW IP blocks. This panel session will debate the merits of these seemingly incompatible proposed SoC methodologies. Pierre Bricaud, Mentor Graphics, Sophia Antipolis, FranceObviously there is no one proper SoC design methodology. You don't design 3G GSM systems as you would Set Top Boxes or Graphics SoCs . But there is a proper design methodology and process to ensure that the components you will use for your SoC integration and verification meet your time to market and cost objectives. The key to this process is to use Reusable IPs and do a proper test and verification plan during SoC specifications . This implies that whatever form of the IP, Soft-Firm-Hard, it must be reusable to a known and accepted methodology, for example RMM and a well defined system verification software and hardware environment. Our contention that today the only complete pratical next generation digital SoC verification environment is based on hardware emulation that accomodates all representations of the IP, synthesizable testbenches and nonsynthesizable testbenches, in-circuit emulation, software debugging, various memory configurations . The higher level of abstraction model or flexible PCB solutions cannot offer a valid solution for the next millinium SoCs .

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