Many supervised machine learning algorithms require a discrete feature space. In this paper, we review previous work on continuous feature discretization, identify de ning characteristics of the methods, and conduct an empirical evaluation of several methods. We compare binning, an unsupervised discretization method, to entropy-based and purity-based methods, which are supervised algorithms. We found that the performance of the Naive-Bayes algorithm signi cantly improved when features were discretized using an entropy-based method. In fact, over the 16 tested datasets, the discretized version of Naive-Bayes slightly outperformed C4.5 on average. We also show that in some cases, the performance of the C4.5 induction algorithm signi cantly improved if features were discretized in advance; in our experiments, the performance never signi cantly degraded, an interesting phenomenon considering the fact that C4.5 is capable of locally discretizing features.

Data mining algorithms including maching learning, statistical analysis, and pattern recognition techniques can greatly improve our understanding of data warehouses that are now becoming more widespread. In this paper, we focus on classification algorithms and review the need for multiple classification algorithms. We describe a system called [Formula: see text], which was designed to help choose the appropriate classification algorithm for a given dataset by making it easy to compare the utility of different algorithms on a specific dataset of interest. [Formula: see text] not only provides a workbench for such comparisons, but also provides a library of C++ classes to aid in the development of new algorithms, especially hybrid algorithms and multi-strategy algorithms. Such algorithms are generally hard to code from scratch. We discuss design issues, interfaces to other programs, and visualization of the resulting classifiers.

No abstract

Over the past year two distinct answers have emerged regarding SoC design methodologies. On the one hand, it is posited in the Reuse Methodology Manual, that a logic synthesis-based design methodology can be used effectively to develop system chips. An alternative methodology focuses on integration (or "reference") platforms and the customization of the basic application-specific platform through the addition of selected SW and/or HW IP blocks. This panel session will debate the merits of these seemingly incompatible proposed SoC methodologies. Pierre Bricaud, Mentor Graphics, Sophia Antipolis, FranceObviously there is no one proper SoC design methodology. You don't design 3G GSM systems as you would Set Top Boxes or Graphics SoCs . But there is a proper design methodology and process to ensure that the components you will use for your SoC integration and verification meet your time to market and cost objectives. The key to this process is to use Reusable IPs and do a proper test and verification plan during SoC specifications . This implies that whatever form of the IP, Soft-Firm-Hard, it must be reusable to a known and accepted methodology, for example RMM and a well defined system verification software and hardware environment. Our contention that today the only complete pratical next generation digital SoC verification environment is based on hardware emulation that accomodates all representations of the IP, synthesizable testbenches and nonsynthesizable testbenches, in-circuit emulation, software debugging, various memory configurations . The higher level of abstraction model or flexible PCB solutions cannot offer a valid solution for the next millinium SoCs .