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This presentation introduces the practice of focused ion beam (FIB) chip editing and its power and versatility as a problem-solving tool. It begins with a review of the features and functions of FIB systems, the role of gas chemistry in milling, etching, and deposition, and the use of IR imaging for navigation and targeting. It goes on to identify challenges due to packaging materials, chip-package interactions, and other factors, and in each case, provide alternate approaches and procedures to circumvent potential problems. It also covers advanced practices and methods and assesses potential future advancements.

The sample preparation required for a typical backside circuit edit (CE) is a significant barrier for some labs, as it requires specific hardware and considerable operator expertise. There are also instances in which it is not possible to mechanically thin the silicon in the typical fashion. This paper addresses the possibility of backside CE be performed on full-thickness silicon devices and the possibility of skipping off the thinning step, as well as the advantages and disadvantages of this approach. Sample trenches are shown, and trenching optimization experiments are described. The paper addresses the issues of navigation, including IR imaging through full-thickness silicon, and how it depends on the sample doping levels. Finally, it presents data on a novel navigational technique that can be employed to improve targeting accuracy. The paper shows that backside CE on full-thickness silicon devices is possible despite the challenges.

This paper introduces a high volume and fast turnaround TEM sample preparation method and requirements for a 300 mm inline DualBeam (FIB/SEM) system with “hands-off” full automation. It requires a factory automation system, robust automated recipes, and an ex-situ TEM lamella liftout system. It describes the recipe structure and TEM lamella lift out procedures. The focus is on fully automated TEM sample preparation for process monitoring in manufacturing line. Two successful examples are described to demonstrate the benefit of this method. The first one is TEM sample for CA profile at M1 level. The second is TEM sample for poly crystalline (PC) line profile at post-etch.