The sample preparation required for a typical backside circuit edit (CE) is a significant barrier for some labs, as it requires specific hardware and considerable operator expertise. There are also instances in which it is not possible to mechanically thin the silicon in the typical fashion. This paper addresses the possibility of backside CE be performed on full-thickness silicon devices and the possibility of skipping off the thinning step, as well as the advantages and disadvantages of this approach. Sample trenches are shown, and trenching optimization experiments are described. The paper addresses the issues of navigation, including IR imaging through full-thickness silicon, and how it depends on the sample doping levels. Finally, it presents data on a novel navigational technique that can be employed to improve targeting accuracy. The paper shows that backside CE on full-thickness silicon devices is possible despite the challenges.

This paper describes a circuit editing procedure in which the authors used a gallium column Focused Ion Beam (FIB) tool to divide a merged 32nm multi-finger planar transistor into two separate operating components. Rather than rely on live imaging or the various endpoint detection techniques commonly used during an active mill, the authors opted for a ‘blind’ dose-driven technique. The paper explains how the authors made multiple attempts on practice material in order to determine the exact beam placement location and the depth of cut required to perform the operation with a minimum of lateral damage. The loss of a pair of poly gate fingers in the middle of the multi-gate structure seemed to have minimal impact on the final electrical parameters and the separate data paths worked per design specifications.

FIB techniques have provided a means for the nanometer-scale spatially confined etching and deposition processes required during repair or editing of advanced integrated circuit (IC) prototypes and lithographic masks. Primary sample properties that can lead to limitations on the applicability of FIB for IC repair are the material composition, aspect ratio, and feature packing density. The typical aims when developing a gas-assisted-etch (GAE) process for IC repair applications are enhancement of etch rate, increased volatilization of reaction products, and improved material selectivity. This paper presents results from a novel two-step process for clearing large areas of one micron thick (upper-level metal) layers. Better equalization of etch rates was achieved using the novel developed FIB GAE process. The paper describes the preliminary results obtained using non-gallium-ion beam based approaches for controlled surface modification during the editing of IC repair samples.

The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static random access memory (SRAM) electrical testing. The embedded memory blocks on some processors are fully configured and probe pad testable as early as the forth metal level. Using a unique navigation technique that combines electrically sorted SRAM bit map data with CAD coordinate information and stage driven X-Y stepping, the FIB tool was used to locate, section and image prior level defects. We believe that with the inclusion of suitable fiducial markers in the chip design and advanced pattern recognition to aid navigation and guide depth milling, a fully automated process for electrical yield detractor diagnosis could be introduced.

Focused Ion Beam (FIB) circuit edit allows for rapid prototyping of potential semiconductor design changes without the need to run a full manufacturing cycle in a semiconductor Fab. By FIB editing a completed module, thorough testing on the bench or in a full system can be achieved. Logic can be toggled, validation of speed enhancements performed, and constructive and destructive failure analysis can be enabled. In order to fulfill all the needs of clients in a rapidly evolving SOC driven market, simply modifying existing devices by “rewiring” circuits is becoming insufficient. Often the team is tasked with making very repeatable structures to aid the circuit analysis group. These include relatively precise resistors for tuning RF circuits (part of an RC network), adding known loads or delays, et cetera. Naturally resistive FIB deposited metal lines connected to the existing circuitry can be used in this capacity. FIB chip edit is considered to be a “Direct Write” process. The beam pattern in conjunction with process gases defines the regions of milling and deposition. Unfortunately, FIB edit is rarely an exact science. In many cases, a number of characteristics seem to be outside the realm of precise repeatable control. This is evident not only in individual tool operational logs but also in FIB tool matching, where maintaining identical system performance within the lab is difficult or nearly impossible. These characteristics are highly dependent on precursor reservoir composition and flow, surface adsorption conditions, beam patterning integrity, and the total interaction space of competing back sputtering during the new material structure formation. Due to these factors, the shape, composition and electrical performance of metal and insulator depositions vary over an often unacceptable range. As a result, we were not meeting the needs of some critical customer applications. Direct written precision resistive structures displayed several issues for which iterative edits were required to compensate for variability. When attempting to create an exact resistance, this process was not reliable, nor was it repeatable enough for accurate circuit performance trimming. Space-constrained serpentine resistors or multiple discrete resistors side-by-side showed the greatest process variability. Metal deposition processes tend to be somewhat self-limiting, so thick boxprofile lines are difficult to form. Conductive material deposited outside of the pattern definition (overspray) results in line-to-line leakages. Attempts to remove the overspray thru ion beam assisted etch-back tends to damage the deposited conductors and underlying insulators. The low-k region between lines can become cross-linked, experience gallium doping, and become tungsten impregnated. This lowered the resistivity of the insulator, increased the resistivity of the conductor, and produced variability in the device which was especially an issue when dealing with varying initial substrates. GLOBALFOUNDRIES began a project to create a more robust repeatable resistive structure by removing several variables. Rather than direct writing lines onto a top surface layer, a confined deposition based on the concepts of dual damascene processing used with copper layers in modern semiconductor fabrication will be employed. The damascene process begins with the definition of a box to be filled with a conductive material. The process of ion beam gas assisted anisotropic etching/milling has a far more predictable outcome than ion beam induced deposition. It is possible to create a surface box mill or even a deep drilled via of desired dimensions with a more consistent repeatability. Deposition of tungsten into a confined region using, for example, a W(CO)6 precursor and a Ga+ ion beam results in an excellent via fill. Using this behavior, precision resistors can be created with metal deposition within the trenches which are created by the gas assisted mill. An enclosed space can be filled nearly void-free, and has repeatable electrical parameters. The self-limiting factors with tungsten deposition go away as sputtered material becomes trapped within the well resulting in a near limitless Zheight potential. The constant dielectric with a uniform and contained tungsten fill can allow for a well-defined resistivity for the FIB deposited tungsten material. Having a known resistivity, calculation of dimensions for resistive and inductive structures during the design process becomes feasible. With process variability under control, structures can be formed reliably enough to offer this as a service to customers.