Semiconductor Test Site structures were analyzed using an EBIRCH (Electron Beam Induced Resistance CHange) system. Localization of a RX (active area) to PC (gate) short was achieved with resolution that surpassed that of OBIRCH (Optical Beam Induced Resistance CHange). A voltage breakdown test structure at Metal 1 was stressed in the system, giving isolation to the specific contact. A five-fin diode macro was examined, and it is believed that the electrically active diffusions were imaged as individual fins from Metal 1. A series of ring oscillator devices were examined in steady state condition, and careful consideration of the image supports a hypothesis that Seebeck effect, from heating material interfaces in an EBIRCH system, is the reason for the “dipoles” reported in earlier literature.

The presence of a full wafer dual-beam FIB on the process floor gave rise to an environment in which formerly segregated off-line lab and FAB tasks could be linked. One such idea involved a methodology for semi-automated defect targeting based on the spatial predictions of static random access memory (SRAM) electrical testing. The embedded memory blocks on some processors are fully configured and probe pad testable as early as the forth metal level. Using a unique navigation technique that combines electrically sorted SRAM bit map data with CAD coordinate information and stage driven X-Y stepping, the FIB tool was used to locate, section and image prior level defects. We believe that with the inclusion of suitable fiducial markers in the chip design and advanced pattern recognition to aid navigation and guide depth milling, a fully automated process for electrical yield detractor diagnosis could be introduced.