We report for the first time a highly selective CVD Co deposition on Cu to fill a 45nm diameter 3:1 aspect ratio via in a Cu dual damascene structure. We have achieved void free Co fill of the via, demonstrating that a selective bottomup via fill with Co is a potentially viable approach. Defect formation and control in the process and device integration are discussed. This selective process provides an opportunity to reduce via resistance and shrink the minimum metal 1 (M1) area for aggressive standard cell size scaling as needed for 7nm technology.

TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N2plasma is not efficient enough to suppress the residue completely [6], and the CH4treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

Low-pH titanium nitride (TiN) removal formulations utilizing oxidizers other than hydrogen peroxide (H 2 O 2 ) have been developed with superior TiN selectivity toward W and the interlevel dielectric (ILD) films. One critical challenge is protecting the TiN barrier layer between the W and dielectric layer, which is often exposed during the TiN metal hard mask (MHM) removal step. This study focused on developing and optimizing formulations with TiN MHM etch rates ≥ 100 Å/min at temperatures ≤ 60 o C, with compatibility toward W, ILD films, and the TiN liner. The galvanic corrosion was tailored to protect the TiN liner in the presence of W. A simple yet novel patterned wafer test vehicle was developed to facilitate this work, enabling the investigation of the chemical impact at the W/TiN liner interface.

Titanium nitride (TiN) is widely used as a hard mask film protecting the inter-level dielectric (ILD) before metal or plating seed layer deposition steps. It is common practice to use a wet etch in order to remove residues formed during the ILD dry-etch step, and at the same time to remove some or all of the exposed TiN. From its thermochemical properties, it might be predicted that wet etching of TiN should be easy, since it is quite unstable with respect to both plain and oxidative hydrolysis. For example, in acidic solutions at 25°C [1, :

In the BEOL, as interconnect dimensions shrink and novel materials are used, it has become increasingly difficult for traditional PERR removal chemicals to meet the evolving material compatibility requirements. As a result, formulated cleans that specifically target these unique challenges are required. Two formulated BEOL cleans were evaluated on blanket and patterned wafer coupons for their ability to wet etch titanium nitride (TiN) and clean post-plasma etch residue, while remaining compatible to interconnect metals (Cu and W) and low-k dielectric (k = 2.4). Both, showed an improvement in material compatibility relative to dilute HF, while simultaneously being able to remove the TiN hardmask and post-etch residue, leading > 90% yield on test structures of varying sizes.