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In this paper we propose a flexible 4-moduli set (2 p+k , 2 p +1, 2 p -1, 2 2p +1) which is profitable to construct a high-speed residue number system (RNS). We derive a simple reverse conversion algorithm for the proposed moduli set by using Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adders which are suitable to realize an efficient VLSI implementation. Based on TSMC 0.13um CMOS technology, the proposed reverse converter demonstrates its superiority in terms of area, delay and power over the converter design for the 4-moduli set (2 n , 2 n -1, 2 n +1, 2 2n +1) under the various dynamic range (DR) requirements. Finally, the chip area, the clock rate and the power consumption of the proposed 32-bit reverse RNS converter are 1227x1227um 2 , 105MHz and 1.3mW respectively.

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In this paper, a systematic compensation approach is presented to efficiently design the approximate squaring function with a simple combinational logic circuit. Also, a set of recursive Boolean equations for general outputs is derived such that the logic circuit can be rapidly designed and reused for various bit-width inputs. In logic implementation, our design approach possesses less circuit cost and lower critical delay. Moreover, in error analysis, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are significantly improved by at least 26.95% and 61.59%, respectively, as compared with the existing approaches. Finally, a 7-bit approximate squaring function chip is accomplished to verify the circuit performance based on 0.6-m CMOS technology. The chip layout occupies 127 135 m 2 and the total number of transistors is 186.

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