Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)

Lin, Su-Hon; Sheu, Ming‐Hwa; Wang, Chao-Hsiang

doi:10.1093/ietisy/e91-d.7.2058

Cited by 22 publications

(10 citation statements)

References 6 publications

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“…Mapping from the RNS system to integers is performed by the Chinese reminder theorem (CRT) [34,41,42]. The CRT states that binary/decimal representation of a number can be obtained from its RNS if all elements of the moduli set are pairwise relatively prime.…”

Section: Residue Number Systemmentioning

confidence: 99%

“…We assume that this interval is sufficient to map the input values, which does not exceed AE2. Third, the reverse converter unit is simple and regular [42] due to using simple circuits design.…”

Section: Residue Number Systemmentioning

confidence: 99%

“…The Chinese remainder theorem (CRT) [34] provides the theoretical basis for converting a residue number into a natural integer. The moduli set P n ¼ 2 n À 1; 2 n ; 2 nþ1 À 1 ÈÉ can be efficiently implemented by four modulo adders and two multiplexers [42]. The output of the RBC is unsigned (3*n +1 )-bits integer number.…”

Section: The Reverse Convertermentioning

confidence: 99%

See 2 more Smart Citations

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

Alzaq¹,

Üstündağ²

2018

Wavelet Theory and Its Applications

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Using discrete wavelet transform (DWT) in high-speed signal-processing applications imposes a high degree of care to hardware resource availability, latency, and power consumption. In this chapter, the design aspects and performance of multiplierless DWT is analyzed. We presented the two key multiplierless approaches, namely the distributed arithmetic algorithm (DAA) and the residue number system (RNS). We aim to estimate the performance requirements and hardware resources for each approach, allowing for the selection of proper algorithm and implementation of multi-level DAA-and RNS-based DWT. The design has been implemented and synthesized in Xilinx Virtex 6 ML605, taking advantage of Virtex 6's embedded block RAMs (BRAMs).

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Section: Residue Number Systemmentioning

confidence: 99%

Section: Residue Number Systemmentioning

confidence: 99%

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A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

Alzaq¹,

Üstündağ²

2018

Wavelet Theory and Its Applications

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“…Moduli set choice is an important issue since the complexity and the speed of the resulting conversion algorithm depend on the chosen moduli set. Several structures have been proposed to perform the reverse conversion for different moduli sets, e.g., {2 n , 2 n − 1, 2 n + 1} [1], {2 n , 2 n+1 − 1, 2 n −1} [3], [2].In [3], the moduli set {2 n+1 −1, 2 n , 2 n − 1} was proposed, by the elimination of the modulus (2 n + 1) from the 4-moduli set {2 n − 1, 2 n , 2 n + 1, 2 n+1 − 1} proposed in [6]. The motivation for this is related to the fact that the modulo (2 n + 1)-type arithmetic is more complex and degrades the entire RNS performance, both in terms of area cost and conversion delay.…”

Section: Introductionmentioning

confidence: 99%

An improved RNS reverse converter for the {22n+1−1, 2n, 2n−1} moduli set

Gbolagade

Chaves

Sousa

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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In this paper, we propose a novel high speed memoryless reverse converter for the moduli set {2 2n+1 − 1, 2 n , 2 n − 1}. First, we simplify the traditional Chinese Remainder Theorem in order to obtain a reverse converter that only requires arithmetic mod-(2 2n+1 − 1). Second, we further improve the resulting architecture to obtain a purely adder based reverse converter. The proposed converter has a critical path delay of (7n + 7) Full Adders (FA) while the best state of the art converter for this moduli set requires (10n + 5) FA on the critical path. To validate these results, the converters are implemented in a Standard Cell 0.18-µm CMOS technology and the results assert that, on average, the proposed converter achieves about 19% delay reduction at the expense of less than 3% area increase.978-1-4244-5309-2/10/$26.00 ©2010 IEEE

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“…The 3n-bit DR moduli sets are {2 n − 1, 2 n , 2 n + 1} [15], {2 n−1 − 1, 2 n − 1, 2 n } [16], and {2 n − 1, 2 n , 2 n+1 − 1} [17], [18]. The DR provided by these moduli sets is not sufficient for applications which require larger dynamic range.…”

Section: Introductionmentioning

confidence: 99%

Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n -1, 2n+1 -1} and {22n, 2n -1, 2n-1 -1}

Molahosseini

Dadkhah

Navi

et al. 2009

IEICE Trans. Inf. & Syst.

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SUMMARYIn this paper, the new residue number system (RNS) moduli sets {2 2n , 2 n −1, 2 n+1 −1} and {2 2n , 2 n −1, 2 n−1 −1} are introduced. These moduli sets have 4n-bit dynamic range and well-formed moduli which can result in high-performance residue to binary converters as well as efficient RNS arithmetic unit. Next, efficient residue to binary converters for the proposed moduli sets based on mixed-radix conversion (MRC) algorithm are presented. The converters are ROM-free and they are realized using carry-save adders and modulo adders. Comparison with the other residue to binary converters for 4n-bit dynamic range moduli sets shown that the presented designs based on new moduli sets {2 2n , 2 n − 1, 2 n+1 − 1} and {2 2n , 2 n − 1, 2 n−1 − 1} are improved the conversion delay and result in hardware savings. Also, the proposed moduli sets can lead to efficient binary to residue converters, and they can speed-up internal RNS arithmetic processing, compared with the other 4n-bit dynamic range moduli sets. key words: residue to binary converter, mixed-radix conversion (MRC), residue number system (RNS), computer arithmetic

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Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)

Cited by 22 publications

References 6 publications

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

An improved RNS reverse converter for the {2<sup>2n+1</sup>−1, 2<sup>n</sup>, 2<sup>n</sup>−1} moduli set

Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n -1, 2n+1 -1} and {22n, 2n -1, 2n-1 -1}

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Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1)

Cited by 22 publications

References 6 publications

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

A Comparative Performance of Discrete Wavelet Transform Implementations Using Multiplierless

An improved RNS reverse converter for the {2<sup>2n&#x002B;1</sup>&#x2212;1, 2<sup>n</sup>, 2<sup>n</sup>&#x2212;1} moduli set

Efficient MRC-Based Residue to Binary Converters for the New Moduli Sets {22n, 2n -1, 2n+1 -1} and {22n, 2n -1, 2n-1 -1}

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An improved RNS reverse converter for the {2<sup>2n+1</sup>−1, 2<sup>n</sup>, 2<sup>n</sup>−1} moduli set