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Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.

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Nondestructive measurement of three-dimensional subsurface features remains one of the most difficult and unmet challenges faced during the fabrication of three-dimensional transistor architectures, especially nanosheet and nanowire based field effect transistors. The most critical fabrication step is the selective etching of silicon-germanium subsurface layers. The resulting shape and dimensions of the remaining Si(1 − x)Gex structure strongly impacts further processing steps and ultimately the electrical performance of gate-all-around transistors, thus creating the need for accurate inline metrology. In order to demonstrate the ability to characterize this etch, nanowire test structures made from Si(1 − x)Gex/Si/Si(1 − x)Gex/Si/Si(1 − x)Gex/Si multilayers have been characterized using Mueller matrix spectroscopic ellipsometry based scatterometry. Transmission electron microscopy images were used to corroborate the authors’ scatterometry measurements. Here, they successfully demonstrate the ability to measure the Si(1 − x)Gex etch, providing an industrially viable technique for inline three-dimensional metrology.