Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Durfee, Curtis; Kal, Subhadeep; Pancharatnam, S.; Bhuiyan, Mansurul; Otto, Ivo; Flaugh, Matthew; Smith, Jeffrey S.; Chanemougame, D.; Alix, Cheryl; Zhou, Huimei; Frougier, Julien; Greene, Andrew; Belyansky, M.; Watanabe, Kôji; Zhang, Jingyun; Schmidt, Daniel; Breton, Mary; Zhao, Kai; Wang, Miaomiao; Basker, Veeraraghavan; Mosden, Aelan; Loubet, N.; Guo, Dechao; Biolsi, Peter; Haran, Bala; Bu, H.

doi:10.1149/10404.0217ecst

Cited by 7 publications

(10 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Nanosheet (NS) gate-all-around (GAA) devices require robust formation of inner spacers and channels for good yield and device performance with low variability (Fig. 1) (1)(2)(3)(4)(5)(6). The Inner Spacer (IS) Indent and Channel Release (CR) etch process steps are quintessential in the integration of GAA NS devices for current and future NS technology nodes (1)(2)(3).…”

Section: Introductionmentioning

confidence: 99%

“…1) (1)(2)(3)(4)(5)(6). The Inner Spacer (IS) Indent and Channel Release (CR) etch process steps are quintessential in the integration of GAA NS devices for current and future NS technology nodes (1)(2)(3).…”

Section: Introductionmentioning

confidence: 99%

“…Since the etch is a timed etch without an etch stop, the indent process must be well-controlled for good within-wafer Lg uniformity. The shape of the IS is an important feature in reducing epitaxial source-drain (S/D) damage during CR (1)(2)(3). A rounded shape allows etch paths around the IS that damage the S/D, while a square shape eliminates this damage mechanism, becoming more important as the IS depth is scaled with subsequent technology nodes (3)(4)(5)(6)(7)(8)(9)(10).…”

Section: Introductionmentioning

confidence: 99%

“…High selectivity of the IS process is critical to limit Si erosion in the extension region. Low selectivity leads to corner rounding and thinner Si, increasing on-resistance (Ron) and overlap capacitance (Cov) (1,2).…”

Section: Introductionmentioning

confidence: 99%

“…A highly-selective CR process is necessary to create uniform channels with smooth Si surfaces and no residual Ge with minimal corner rounding (2). Exceptional selectivity to the spacer (Sp0), IS and Si channels is required for good yield (1,3).…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Durfee,

Otto IV,

Kal

et al. 2023

ECS Trans.

View full text Add to dashboard Cite

Nanosheet gate-all-around devices have demonstrated several advantages in device performance and area scaling over finFET devices with higher device density and improved electrostatic control. Robust inner spacer (IS) and channel formation is critical for high performance, reduced variability and good yield. An isotropic dry etch of the sacrificial SiGe layer with extremely high selectivity to gate spacer, IS and Si channels is necessary for high-quality channel formation over a wide range of sheet widths. Furthermore, the nFET Si:P and pFET SiGe:B source-drain (S/D) epitaxy must be isolated using inner spacers or buffers to prevent damage during Channel Release (CR). The damage can be further mitigated with optimized CR etch chemistry, enabling IS scaling. We highlight S/D damage mechanisms during CR, then demonstrate reduced S/D damage by co-optimization of the IS, CR chemistry and S/D epitaxy.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Durfee,

Otto IV,

Kal

et al. 2023

ECS Trans.

View full text Add to dashboard Cite

show abstract

Loading Effect during SiGe/Si Stack Selective Isotropic Etching for Gate-All-Around Transistors

Shao,

Reiter,

Chen

et al. 2024

ACS Appl. Electron. Mater.

View full text Add to dashboard Cite

The loading effect hinders the precise profile control during the selective etching of SiGe in stacked SiGe/Si layers, thereby hindering optimal gate-all-around (GAA) transistor performance. In this article, we present a systematic study on the loading effect in the selective isotropic etching of SiGe in SiGe/Si stacks by varying the structure density and process conditions, including chamber pressure and etch time. We measure the lateral SiGe etching depth at different locations within the stack pillars and evaluate the local etch uniformity. The results demonstrate that pressure plays an important role in affecting the isotropic lateral etching performance. Within the tested 10–40 mTorr range, higher pressures lead to increased etch rates but at the cost of reduced uniformity. A noteworthy observation is that the uniformity also decreases as the process time increases. To understand and quantify the phenomena, we propose a physical etch model based on top-down Monte Carlo ray tracing and simulate the etch profiles. We calibrate the model with measured data on less dense pillar arrays with 100 nm spacing and achieve small prediction error on denser pillars with a spacing of 50 nm. The good agreement between simulations and experiments demonstrates that the restriction of particle diffusion in the narrow gap is the major contributor to the loading effect, and our model is capable of quantitatively characterizing this phenomenon by predicting the lateral etching profile. This research provides valuable insights into the etching effects through experiments and theoretical studies in order to promote the advanced etching technology development toward GAA transistor manufacturing.

show abstract

Novel structure of Fin-iTFET with main gate and source metal formed simultaneously while control gate and drain formed simultaneously

Lin,

Lin

2024

Phys. Scr.

View full text Add to dashboard Cite

In this paper, we propose a new structure for Fin-iTFET where the main gate and source metal are formed simultaneously, and the control gate and drain are formed simultaneously. The process used for the realization is simple, costless, and fully compact with conventional CMOS technology. With the help of a control gate, our Fin-iTFET can achieve a steep subthreshold swing (SSavg) and a high ION/IOFF ratio. Using Sentaurus TCAD simulations, we confirm that the current transport mechanism of our Fin-iTFET is based on band-to-band line-tunneling, which enhances the ON current (ION) and mitigates leakage with a reduced trap-assisted tunneling (TAT) effect. Instead of relying on dopant implantations and thermal annealing, we utilize a metal-semiconductor Schottky junction to enhance the minority carrier concentration at the source end, increase band bending, increase the overlap between the conduction band and valence band, increase the vertical electric field, and thereby increase the line tunneling generation rates, ultimately enhancing the ON current of the device. The simulations show that the device exhibits an SSavg of 13.6 mV/dec with an ION/IOFF ratio of 10⁹ at VD = -0.2V and VCG = 0.2V. In short, our Fin-iTFET can achieve excellent electrical performance at low power supply voltages.

show abstract

Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Cited by 7 publications

References 10 publications

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors

Loading Effect during SiGe/Si Stack Selective Isotropic Etching for Gate-All-Around Transistors

Novel structure of Fin-iTFET with main gate and source metal formed simultaneously while control gate and drain formed simultaneously

Contact Info

Product

Resources

About