Scan Compression has become the default design-for-test (DFT) methodology for achieving high quality test at lower costs. Just as scan matured over a span of 40 years we are now observing Scan Compression improving and adapting to the needs of current designs. In this paper we present an industrial case study demonstrating how the DFT flows are impacted in the presence of compression logic for test. We develop various DFT architectures using the zScan compression technology and discuss the pros and cons of each flow w.r.t. pin limited test and modular DFT insertion. We also show that the decisions of pin count and scan chain count dramatically impact the final QoR i.e., test application time and test data volume required to test the chip.

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With chip designs continuously shrinking nodes and new fault models evolving for lower nodes, scan compression based testing has become the standard test methodology. There are many papers on the implementation of Scan Compression. All these papers discuss the implementation of the technology in an idealistic environment. In this paper we present design issues that impact the overall scan compression architecture. This paper is an example of an industrial environment and the decisions that impact scan compression. Results of the implementation are presented with data.

As scan compression matures, the focus is changing from delivering QoR to other pressing requirements like hierarchical DFT implementation, pin-limited test and enabling high speed shifting of scan chains. Combinational compression schemes have had great success in the last decade in delivering a solution that provided a fast transition from traditional scan based test to compression based test. In this paper, a more efficient combinational test compression technique called zScan is presented. We show that this technology is able to meet tough requirements demanded by todays system-on-a-chip (SoC) designs while delivering competitive test data volume and test application time reduction.