Many dynamic scheduling algorithms have been proposed in the past. With the advent of multi core processors, there is a need to schedule multiple tasks on multiple cores. The scheduling algorithm needs to utilize all the available cores efficiently. The multicore processors may be SMPs or AMPs with shared memory architecture. In this paper, we propose a dynamic scheduling algorithm in which the scheduler resides on all cores of a multi-core processor and accesses a shared Task Data Structure (TDS) to pick up ready-to-execute tasks. This method is unique in the sense that the processor has the onus of picking up tasks whenever it is idle. We have discussed the proposed scheduling algorithm using a set of tasks as an example.The paper concludes with the discussion of advantages and limitations of the proposed scheduling algorithm.

No abstract

Abstract. This paper presents highly optimized implementation of image registration method that is invariant to rotation scale and translation. Image registration method using FFT works with comparable accuracy as similar methods proposed in the literature, but practical applications seldom use this technique because of high computational requirement. However, this method is highly parallelizable and offloading it to the commodity graphics cards increases its performance drastically. We are proposing the parallel implementation of FFT based registration method on CUDA and OpenCL. Performance analysis of this implementation suggests that the parallel version can be used for real time image registration even for image size up to 2k x 2k. We have achieved significant speed up of up to 345x on NVIDIA GTX 580 using CUDA and up to 116x on AMD HD 6950 using OpenCL. Comparison of our implementation with other GPU based registration method reveals that our implementation performs better compared to other implementations.

Multicore processors have paved the way to increase the performance of any application by the virtue of benefits of parallelization. However, exploiting parallelism from a program is not easy, as it requires parallel programming expertise. In addition, manual parallelization is a cumbersome, time consuming and inefficient process. A number of tools proposed in the past ease the effort of parallel programming. This paper presents a classification of such parallelization tools. The classification is based on different eras of tool development, role playedby these tools in various parallelization stages, and features provided by parallel program assistance tools. Classification of tools concludes with a discussion on requirements of futuristic parallelization tools. Finally, this paper proposesour on-going work about the development of a parallel program assistance tool called EasyPar, which is a parallel program assistance tool.

Stereo matching technique is used to estimate the depth of objects in an image acquired from real time scenes. The basic algorithm is not very complex but is computationally exhaustive and hinders its usage for real time applications. However, this algorithm is highly data parallel and it highly suitable for execution on GPGPU (General-purpose graphical processing units). In this paper, we are proposing the parallel implementation of the fast stereo matching algorithm based on correlation of multi-resolution images using CUDA (Compute Unified Device Architecture). The performance of this implementation is faster than most of the software implementations of this method and comparable with FPGA implementation and few other optimized methods mentioned in the references. This enables the real time usage of stereo matching method. We have also provided performance comparison and results for different methods of stereo matching on CUDA. The paper concludes with analysis of results and the reasons of the performance variations. We have also given qualitative image data for comparison of accuracy of different stereo correspondence methods.