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In the context of RESTful web-services, connectedness refers to the property wherein every resource in the web-service is reachable from the base resource by successive HTTP GET requests. Presence (or absence) of connectedness has practical implications and hence is an important property of RESTful web-services. In this article, we present an algorithm for testing the connectedness of RESTful webservices. Using a formal specification of the web-service, our algorithm tests the connectedness of a web-service automatically. We also discuss a formal notation we have developed to specify RESTful web-services. Using our notation, we wrote the formal specification for a prototype RESTful web-service which has been developed for internal use in our organisation. Using this specification we employed our method to conduct automated testing of the above webservice. Many functional defects apart from those related to connectedness were detected early during development. This demonstrated that both our specification notation and our testing method are promising innovations in the direction of specification and testing of RESTful web-services.

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Power dissipation and tolerance to process variations pose conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor up-sizing for process tolerance can be detrimental for power dissipation. However, for certain signal processing systems such as those used in color image processing, we noted that effective trade-offs can be achieved between Vdd scaling, process tolerance and "output quality". In this paper we demonstrate how these tradeoffs can be effectively utilized in the development of novel low-power variation tolerant architectures for color interpolation. The proposed architecture supports a graceful degradation in the PSNR (Peak Signal to Noise Ratio) under aggressive voltage scaling as well as extreme process variations in sub-70nm technologies. This is achieved by exploiting the fact that some computations are more important and contribute more to the PSNR improvement compared to the others. The computations are mapped to the hardware in such a way that only the less important computations are affected by Vdd-scaling and process variations. Simulation results show that even at a scaled voltage of 60% of nominal Vdd value, our design provides reasonable image PSNR with 69% power savings.

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