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In this paper, we propose the fast frequency settling Phase Locked Loop (PLL) frequency synthesizer utilizing the Frequency Detector Method Speedup Circuit (FDMSC). FDMSC is composed of a Frequency Detector (FD) and a Charge Controller (CC). By CC, the control voltage of Voltage Controlled Oscillator (VCO) is forced to move to the objective value, and once the objective frequency is detected by FD, FDMSC can suppress the transient response of a PLL frequency synthesizer. The effectiveness of the proposed PLL frequency synthesizer is shown through some experiments.

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In this paper, we present a high-efficiency 400 W PA for a 6 MHz OFDM signal with a 10 dB peak-to-average power ratio (PAPR). To improve the efficiency of the PA at a 10 dB backoff from its saturated output power (PSAT), a dynamic drain voltage control is applied, which supplies two different drain voltages depending on the envelope of the OFDM signal. The PA is fabricated using a 400 W pushpull LDMOS FET for an UHF band. The drain current of a single LDMOS FET is 9.5 A at PSAT. The drain voltages used in the control are set to 40 V and 20 V. Measurement results indicate a power-added efficiency (PAE) in the case of dynamic drain voltage control of 34%, which is 15% higher than PAE at a drain voltage of 40 V. This is the highest output power of a PA with a dynamic drain voltage control to the best of our knowledge.