Improvements to perovskite solar cells (PSCs) have focused on increasing their power conversion efficiency (PCE) and operational stability and maintaining high performance upon scale-up to module sizes. We report that replacing the commonly used mesoporous–titanium dioxide electron transport layer (ETL) with a thin layer of polyacrylic acid–stabilized tin(IV) oxide quantum dots (paa-QD-SnO 2 ) on the compact–titanium dioxide enhanced light capture and largely suppressed nonradiative recombination at the ETL–perovskite interface. The use of paa-QD-SnO 2 as electron-selective contact enabled PSCs (0.08 square centimeters) with a PCE of 25.7% (certified 25.4%) and high operational stability and facilitated the scale-up of the PSCs to larger areas. PCEs of 23.3, 21.7, and 20.6% were achieved for PSCs with active areas of 1, 20, and 64 square centimeters, respectively.

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The fabrication of ultrathin silicon wafers at low cost is crucial for advancing silicon electronics toward stretchability and flexibility. However, conventional fabrication techniques are inefficient because they sacrifice a large amount of substrate material. Thus, advanced silicon electronics that have been realized in laboratories cannot move forward to commercialization. Here, a fully bottom‐up technique for producing a self‐releasing ultrathin silicon wafer without sacrificing any of the substrate is presented. The key to this approach is a self‐organized nanogap on the substrate fabricated by plasma‐assisted epitaxial growth (plasma‐epi) and subsequent hydrogen annealing. The wafer thickness can be independently controlled during the bulk growth after the formation of plasma‐epi seed layer. In addition, semiconductor devices are realized using the ultrathin silicon wafer. Given the high scalability of plasma‐epi and its compatibility with conventional semiconductor process, the proposed bottom‐up wafer fabrication process will open a new route to developing advanced silicon electronics.

During the fabrication of crystalline silicon solar cells, kerf-loss caused by the wire-sawing of silicon ingots to produce thin wafers inevitably limits the reduction of electricity production cost. To avoid the kerf-loss, direct growth of crystalline silicon wafers of 50-150 μm with a porous separation layer that can be mechanically broken during the exfoliation process, has been widely investigated. However, several issues including flattening of the surface after the exfoliation remain unsolved. In this work an alternative method that utilizes a water-soluble Sr₃Al₂O₆ (SAO) sacrificial layer inserted between the mother substrate and the grown crystalline silicon layers is introduced. Polycrystalline silicon layers were grown on SAO/Si by plasma-enhanced CVD process and silicon membranes could be successfully obtained after the dissolution of SAO in the water. Same process could be applied to obtain flexible amorphous silicon membranes. Further research is being conducted to increase the size of the exfoliated wafer, which expects to reduce the production cost of crystalline silicon solar cells effectively.

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