This work focuses on the analysis of recent developments and future trends of organic substrates and 2.5D interposers. In the sub 10 μm line/width space, substrate manufacturers are pushing towards traditionally foundry level Si processing dimensions. Latest R&D shows organic substrates with L/S capability down to 2/2 μm. Organic substrates and 2.5D interposers can be in many cases separated in two different groups, however certain solutions propose a combination of the two, such as embedded interposers or fine extension layers of organic substrates acting as interposers. These substrate and interposer architectural solutions are analyzed. Furthermore, organic processing options and latest feature sizes are discussed. Dielectric build up material options with low dielectric constant (Dk) and low tangent loss (Df) are analyzed and their expected thermo-mechanical property trends presented, including the coefficient of thermal expansion (CTE), Young's modulus (E) and glass transition temperature (Tg). Coreless substrates and their advantages, disadvantages, industry readiness and future development are also addressed. Furthermore, 2.5D interposer options are analyzed by type of material: Si, glass and organic. A qualitative and quantitative comparison of their features and market status is done and their future development is extrapolated. Final conclusions are made on the sub 10 μm line/width advanced substrate application space and the market interaction of organic substrates and 2.5D interposers

The Mumbai region in India experienced a massive outage on October 12, 2020, due to cascade failure. The event taught some serious lessons to the grid operators and highlighted the need for energy security and reliability. In this incident, the cascade tripping of the external transmission network resulted in an unexpected island containing Mumbai city isolating it from the rest of Indian power grid. Although the Mumbai islanding scheme was operational, it failed to survive due to high rate of change of frequency (ROCOF). Globally, such blackouts occur due to low probability, high impact events. Major blackouts are caused by a set of triggering events that are usually preceded by some incidents that weaken the power system. Further, the failure of important security mechanisms and protections can compound the effect of disturbances. In view of this, the paper focuses on the consequences of cascading events that led to several blackouts in history. This paper analyses the October 12, 2020, Mumbai power grid failure by recreating various scenarios that resulted in the blackout through dynamic modelling on the PSS/E platform. The results were validated using data collected from phasor measurement units (PMUs) and SCADA. In this article various challenges faced during unfolding of the event are presented. Lessons learnt such as appropriate settings and tuning were identified to ensure the survival of islanding scheme. Assessment of Mumbai power system's transfer capability is done to facilitate the optimal mix of imported and embedded generation.INDEX TERMS Blackout, cascade failure, critical infrastructure, islanding, power system modelling and simulator for engineering (PSS/E), rate of change of frequency (ROCOF), smart grid, under-frequency load shedding.

No abstract

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

In this paper, we present an embedded platform for real-time emulation of nonlinear electrical circuits in an embedded processor. Electrical systems, if complex, are better implemented if split into number of tasks. These tasks will have different priorities and timing deadlines and hence must be managed by an Operating System. We present and evaluate an iteration time based adaptive time step scheduling algorithm in an embedded linux 2.6.29.6 based operating system with Xenomai-HAL 2.5.2 (Hardware Abstraction Layer) in order to manage the various tasks. The paper explores methods to improve the accuracy of the application by reducing the integration time step. The use of ARM EABI cross compiler is also evaluated.