2.5D Interposers and Advanced Organic Substrates Landscape: Technology and Market Trends

Ivankovic, A.; Buisson, Thibault; Kumar, Sunny; Pizzagalli, Amandine; Beica, Rozalia

doi:10.4071/isom-2015-tp22

Cited by 6 publications

(4 citation statements)

References 1 publication

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“…The buildup layer studied was an Ajinomoto buildup film (ABF) by Ajinomoto Fine Techno., Co. (currently in use for PCB mass production ,,, and especially in smartphones assembly). This buildup sheet consists of an epoxy–phenol matrix and spherical glass fillers.…”

Section: Methodsmentioning

confidence: 99%

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Improvements of the Epoxy–Copper Adhesion for Microelectronic Applications

Granado

Kempa

Gregoriades

et al. 2019

ACS Appl. Electron. Mater.

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Upcoming electronic devices are required to be further miniaturized. The microelectronics industry and packaging technology focus efforts on optimizing adhesion between plated copper and printed circuit board (PCB) substrate (here epoxy/glass buildup composite), while keeping smooth surfaces for high-frequency application. We propose herein to review and deepen the basic understanding of the sequential buildup process employed worldwide for the past several decades for multilayered PCB manufacturing. This multiscale and interdisciplinary study aims to establish the relationships between degrees of precuring (α), oxidative etching (permanganate desmear wet treatment), and copper adhesion. The epoxy curing states on industrial coupons were evaluated by diffuse-reflectance infrared Fourier transform spectroscopy. Then, atomic force microscopy (AFM) described the desmear performances through topography evolution with α between the different sequence steps. Finally, polymer−copper adhesions were investigated by using peel strength tests, AFM, and X-ray photoemission spectroscopy. We remark that high adhesion strengths were obtained for very smooth surfaces. This study outlines the contribution of the polymer network viscoelasticity (relaxation dynamic) on the polymer−copper adhesion. We observed that faster polymer relaxation rates tended to increase polymer−copper adhesions.

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Section: Methodsmentioning

confidence: 99%

“…Additionally, high-frequency applications require low surface roughness. Silicon and glass interposers are relevant materials, but they are expensive . Still, a more cost-effective option relies on the improvement of organic buildup (BU) layer performances and their processing optimizations.…”

Section: Introductionmentioning

confidence: 99%

Improvements of the Epoxy–Copper Adhesion for Microelectronic Applications

Granado

Kempa

Gregoriades

et al. 2019

ACS Appl. Electron. Mater.

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“…With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from 2D planar packaging structures to 3D packaging structures. Well-known memory manufacturers, such as Samsung Electronics, Micron, and SK hynix, have further improved the performance of memory devices via the use of 3D packaging technologies, such as PoP (package on package) [1][2][3], CoC (Chipon-Chip) [4][5][6], WLP (Wafer Level Package) [7][8][9], TSV (through-silicon via) [10][11][12], and Embedded Substrate [13][14][15], meeting the industry demands for high-frequency, highspeed, and large-capacity devices with low power consumption.…”

Section: Introductionmentioning

confidence: 99%

Survey of Reliability Research on 3D Packaged Memory

Zhou

et al. 2023

Electronics

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As the core carrier of information storage, a semiconductor memory device is a basic product with a large volume that is widespread in the integrated circuit industry. With the rapid development of semiconductor manufacturing processes and materials, the internal structure of memory has gradually shifted from a 2D planar packaging structure to a 3D packaging structure to meet industry demands for high-frequency, high-speed, and large-capacity devices with low power consumption. However, advanced 3D packaging technology can pose some reliability risks, making devices prone to failure, especially when used in harsh environmental conditions, including temperature changes, high temperature and humidity levels, and mechanical stress. In this paper, the authors introduce the typical structure characteristics of 3D packaged memory; analyze the reasons for device failure caused by stress; summarize current research methods that utilize temperature, mechanical and hygrothermal theories, and failure models; and present future challenges and directions regarding the reliability research of 3D packaged memory.

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“…It is a promising solution to build larger and faster processors with high yield. With the help of the novel 2.5-D integration technology [6] [7], chips can be interposed on a wafer while an inter-chip network is fabricated on the wafer in order to accommodate the communication flows among chips. The inter-chip network is thus called Network-on-wafer(NoW) in this paper, while in some literature they are referred to as inter-chip NoC.…”

Section: Introductionmentioning

confidence: 99%

On the network design and control of an optical network: interconnecting multiple chips on a wafer

Zhang¹,

Colle²,

Tavernier³

et al. 2023

J. Opt. Commun. Netw.

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In this paper, we propose a network architecture for a multi-chip optical network-on-wafer (NoW); we concentrate on the research of its control mechanisms and control algorithms. Our proposed optical NoW aims at providing dynamically controlled terabytes-per-second unidirectional bandwidth for every chip module in a multi-chip processor. This architecture is promising in achieving low energy consumption and high aggregated bandwidth, providing a competitive idea for the next generation of optical-connected multi-chip computing systems. A synchronous network control scheme with a network control algorithm is proposed for slowly varying traffic patterns. Moreover, an edge coloring algorithm is an important part of our network control algorithm; we propose improved edge coloring algorithms modified from existing edge coloring algorithms. We show that our improved edge coloring algorithm has lower time complexity and also achieves faster execution in our experiments than the existing methods.

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2.5D Interposers and Advanced Organic Substrates Landscape: Technology and Market Trends

Cited by 6 publications

References 1 publication

Improvements of the Epoxy–Copper Adhesion for Microelectronic Applications

Improvements of the Epoxy–Copper Adhesion for Microelectronic Applications

Survey of Reliability Research on 3D Packaged Memory

On the network design and control of an optical network: interconnecting multiple chips on a wafer

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