One of the major hurdles in the design of Static Random Access Memory (SRAM) cell is the ever increasing process variations. To counter this researchers have proposed various bit-cell and non-bit-cell oriented designs. However, the proposed techniques require additional circuitry and hence account for large area overhead. In this paper we propose the use of rise time of word-line signal as a measure to reduce the impact of the process variations on the SRAM cells. Simulation results show that using a higher rise time resulted in drastic reduction in the number of cells that fail to read or write. Number of cells that can successfully write or read improved from 82% to 98.2% and 90% to 98.8% respectively. However, there is some speed penalty to achieve this.