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Clock gating is an efficient technique for reducing dynamic power in sequential circuits. It saves power by partitioning the main clock and distributing the clock to the logic blocks only when there is a need for those blocks to be activated. Synchronous circuits show reduced dynamic power dissipation for effective clock gating implementations. The paper tries to investigate different clock gating schemes and implement them to optimize the power dissipation in synchronous designs. These strategies are used to increase the flexibility of an up-to-date SPI master/slave implementation followed by the analysis of power reduction achieved. The whole design is implemented in Verilog 2001 and mapped onto Xilinx Virtex 5 FPGA device.

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