2014 International Conference on Advances in Electrical Engineering (ICAEE) 2014
DOI: 10.1109/icaee.2014.6838431
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Design and implementation of a high speed Serial Peripheral Interface

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Cited by 18 publications
(5 citation statements)
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“…The master FPGA (Red Pitaya) is responsible for receiving orders from PC and control MW source and sampling module (including DAQ and DSP). Except from 3-pin serial peripheral interface (SPI) [ 26 ], the master–slave FPGA is connected by a trigger signal, which could ensure the signal synchronization between signal sampling and microwave generation.…”
Section: Figurementioning
confidence: 99%
“…The master FPGA (Red Pitaya) is responsible for receiving orders from PC and control MW source and sampling module (including DAQ and DSP). Except from 3-pin serial peripheral interface (SPI) [ 26 ], the master–slave FPGA is connected by a trigger signal, which could ensure the signal synchronization between signal sampling and microwave generation.…”
Section: Figurementioning
confidence: 99%
“…O SPI é um protocolo de comunicação síncrono entre microcontroladores que foi adotado devido a operar em altas frequências e mostrar-se rápido e eficiente na transferência de dados [21].…”
Section: Spi -Serial Peripheral Interfaceunclassified
“…SPI can communicate with f duplex and full-duplex methods [4]. SPI communication consists of masters and slaves [5], the master provides SCK to synchronize.…”
Section: Introductionmentioning
confidence: 99%