Abstract-We present OCDIMM (Optically Connected DIMM), a CPU-DRAM interface that takes advantage of multiwavelength optical interconnects. We show that OCDIMM has at least three key benefits when compared to alternatives such as FBDIMM (Fully Buffered DIMM), which is used in recent products from Sun [1] and Intel. First, replacing the multi-hop store-and-forward network in the FBDIMM architecture by a WDM (wavelength-division multiplexing) based optical interconnect results in significantly lower latency (up to 50% reduction in some configurations). Second, it is scalable to much higher capacities (such as 32 DIMMs per channel) with only a modest degradation in latency. Third, due to the higher data rate of an optical interface and the concurrency offered by multiple wavelengths, OCDIMM offers up to a 90% improvement in memory bandwidth. Most importantly, these benefits can be obtained using off-the-shelf DRAM devices, by making simple modifications to the DIMM circuit board and the memory controller.

Abstract-We present OCDIMM (Optically Connected DIMM), a CPU-DRAM interface that uses multiwavelength optical interconnects. We show that OCDIMM is more scalable and offers higher bandwidth and lower latency than FBDIMM (Fully-Buffered DIMM), a state-of-the-art electrical alternative. Though OCDIMM is more power efficient than FBDIMM, we show that ultimately the total power consumption in the memory subsystem is a key impediment to scalability and thus to achieving truly balanced computing systems in the terascale era.

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<p class="MsoNormal" style="text-align: left; margin: 0cm 0cm 0pt; layout-grid-mode: char;" align="left"><span class="text"><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;">Success in the embedded world revolves around two key concepts: cost effectiveness and performance. The ability for an operating system to boot quickly combined with speedy application usage at runtime is important to consumer unit adoption. The most common memory sub-system setup in cellular phone architectures today is what is called an eXecute-In-Place architecture. This type of memory subsystem defines the execution of code and data directly from NOR flash memory. An additional memory architecture of choice is called a Store and Download architecture. This is a memory sub-system where the code gets copied to RAM at boot time and executes out of the RAM. This paper explores the addition of a new memory usage model called a Balanced XIP System. By choosing to use a Balanced XIP System you will save battery life while utilizing system resources. This is important in an age where lifestyle is driven by quick data access and electronic device energy longevity. The result is a system that combines a small RAM memory requirement with a performance increase for improved targeted application and boot time execution.</span></span><span style="font-family: ";Arial";,";sans-serif";; font-size: 9pt;"></span></p>

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