OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects

Hadke, A.; Benavides, T.; Yoo, S. J. B.; Amirtharajah, Rajeevan; Akella, Venkatesh

doi:10.1109/hoti.2008.25

Cited by 27 publications

(20 citation statements)

References 16 publications

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“…For now we assume that a PIDRAM bank never needs to be distributed across multiple chips, and later in this section we will revisit this assumption. Figure 4(a) shows a shared photonic bus, which is similar to several photonic DRAM proposals in the literature [7,24] and logically works like a standard electrical bus. In this implementation, the memory controller first broadcasts a command to all of the banks and each bank determines if it is the target bank for the command.…”

Section: Pidram Channel Organizationmentioning

confidence: 84%

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

Beamer

Sun

Kwon

et al. 2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

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The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of electrical DRAM architectures appears unlikely to suffice, being constrained by processor and DRAM pin-bandwidth density and by total DRAM chip power, including off-chip signaling, cross-chip interconnect, and bank access energy. In this work, we redesign the DRAM mainmemory system using a proposed monolithically integrated siliconphotonic technology and show that our photonically interconnected DRAM (PIDRAM) provides a promising solution to all of these issues. Photonics can provide high aggregate pin-bandwidth density through dense wavelength-division multiplexing. Photonic signaling provides energy-efficient communication, which we exploit to not only reduce chip-to-chip interconnect power but to also reduce cross-chip interconnect power by extending the photonic links deep into the actual PIDRAM chips. To complement these large improvements in interconnect bandwidth and power, we decrease the number of bits activated per bank to improve the energy efficiency of the PIDRAM banks themselves. Our most promising design point yields approximately a 10× power reduction for a single-chip PIDRAM channel with similar throughput and area as a projected future electrical-only DRAM. Finally, we propose optical power guiding as a new technique that allows a single PIDRAM chip design to be used efficiently in several multi-chip configurations that provide either increased aggregate capacity or bandwidth.

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Section: Pidram Channel Organizationmentioning

confidence: 84%

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

Beamer

Sun

Kwon

et al. 2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

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“…Further, with the growing use of high data rate serial links, the SerDes power consumption will continue to decrease [32]. We envision huge power savings by incorporating integrated photonic components [33] in future OCM nodes, gaining benefits from the tighter integration of optical components with electronic driver and receiver circuitry [13][14][15]. Silicon photonics will eliminate the need for any off-chip wiring, such as between an SDRAM chip and a transceiver, improving the overall bandwidth, latency, and energy efficiency.…”

Section: E Architectural Analysis and Discussionmentioning

confidence: 99%

“…OCDIMM [14] is an OCM module based on FB-DIMM, in which silicon photonics realized near the processors and memory modules allow the electronic memory bus to be replaced with waveguides as a shared, wavelength-routed bus. The unique advantage here is improved memory access latency when compared to traditional FB-DIMM.…”

Section: Related Workmentioning

confidence: 99%

Building Data Centers With Optically Connected Memory

Brunina¹,

Lai

Garg

et al. 2011

J. Opt. Commun. Netw.

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Abstract-Future data centers will require novel, scalable memory architectures capable of sustaining high bandwidths while still achieving low memory access latencies. Electronic interconnects cannot meet the challenges presented by the need for multi-terabit off-chip memory data paths. In this work, the electronic bus between main memory and its host processor is replaced with a circuit-switched optical interconnection network. We investigate the impact of our optically connected memory system on large-scale architectures and experimentally validate the protocol using field-programmable gate array based processor nodes and a custom-designed memory controller. The processor communicates all-optically with multiple synchronous dynamic random access memory nodes using 4×2.5-Gb/s wavelength-striped payloads, operating error free with bit-error rates less than 10 −12 .

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“…More complicated physical design (e.g., redundant transmitters and optical power guiding) may have some implications on the electrical control logic and thus the network's microarchitecture, but it is important to note that these techniques are solely focused on mitigating physical design issues and do not fundamentally change the logical network topology. Most nanophotonic buses in the literature use wavelength slicing [1], [2], [4] and there has been some work on the impact of split nanophotonic buses [4], and guided nanophotonic buses [3].…”

Section: Physical-level Designmentioning

confidence: 99%

Designing Chip-Level Nanophotonic Interconnection Networks

Batten

Joshi

Stojanović

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto a single die, but the success of such systems could be limited by the corresponding chip-level interconnection networks. There have been many recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-efficiency compared to electrical networks. This paper discusses the approach we have used when designing such networks, and provides a foundation for designing new networks. We begin by briefly reviewing the basic silicon-photonic device technology before outlining design issues and surveying previous nanophotonic network proposals at the architectural level, the microarchitectural level, and the physical level. In designing our own networks, we use an iterative process that moves between these three levels of design to meet application requirements given our technology constraints. We use our ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor-to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this design process.

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OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects

Cited by 27 publications

References 16 publications

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

Re-architecting DRAM memory systems with monolithically integrated silicon photonics

Building Data Centers With Optically Connected Memory

Designing Chip-Level Nanophotonic Interconnection Networks

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