In this paper a method is presented for the fabrication of micro-channel networks in glass with integrated and insulated gate electrodes to control the zeta-potential at the insulator surface and therewith the electro-osmotic flow (EOF). The fabrication of the electrodes is a sequence of photolithography, etching and thin film deposition steps on a glass substrate, followed by chemical mechanical polishing (CMP) and subsequently direct thermal bonding to a second glass plate to form closed micro-channels. Plasma enhanced chemical vapor deposition (PECVD) SiO 2 -layers as insulating material between the electrodes and microchannels and different electrode materials are examined with respect to a high bonding temperature to obtain an optimal insulating result. A CMP process for the reduction of the SiO 2 topography and roughness is studied and optimized in order to obtain a surface that is smooth enough to be directly bondable to a second glass plate.

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Surface Acoustic Wave (SAW) filters are key components for mobile communication. In SAW devices mechanical waves propagate on the surface of a piezoelectric bulk material such as LiNbO3 or LiTaO3. SAW components require advanced cavity packaging solutions in order to enable the mechanical wave propagation on the substrate material. Size reduction of SAW filters allows further miniaturization of mobile phones and an extension of their functionality. The mobile communication industry, therefore, demands advanced cavity package technologies to be developed for SAW components. These packages have to offer high performance, high reliability, and low cost while maintaining a form factor as small as possible. To address these requirements EPCOS has developed a Die Sized SAW Package (DSSP), a true chip-size wafer level package for SAW filters. This paper discusses the manufacturing process of wafer-level-packages for SAW-devices with a special focus on the adhesive wafer bonding technology.

The novel wafer-level packaging (WLP) process described in this paper allows quasi-hermetic capping of optical devices on wafer-level yielding miniaturized glass cavity windows on top of the optical area, at the same time leaving the contact area accessible for standard electrical connections i.e. wire bond. These smaller chip-size optical cavity packages are used within standard chip-on-board (COB) assemblies for high performance optical applications providing high yield and utmost reliability.In this paper the process flow of generating optical cavity glass wafers as well as of the wafer-level capping process is demonstrated and reliability data on wafer-level and packagelevel are discussed. Fig. 1: Smaller chip size glass cavity window on product wafer I. Wafer-Level Capping of Optical DevicesWafer level packaging of optical devices is becoming more and more mainstream [1]. Beside the overall deciding advantages of cost per die and system yield, performance and reliability targets can be matched for an increasing range of applications.In this paper we disclose the general manufacturing process for capping of devices on wafer level using a microstructured cap wafer. The process yields the uniqueness to bond the caps only on top of the selected areas leaving the exclude areas untouched e.g. for wire bond. This provides an ideal compromise between WLP and classical COB with the advantage that sensitive optical structures are selectively sealed on wafer-level in a very early stage -significantly reducing yield loss due to particle contamination especially well-known for image sensor modules [2]. Furthermore the proposed process provides an increased flexibility for assembly in order to bring costs down.Depending on the method of micro structuring of the cap wafer, the individual caps may provide a cavity for the encapsulated devices. These cavities being obvious and well-known for MEMS are also required for optical applications like MOEMS or image sensors -e.g. if these have micro lenses on the optical area of a camera chip. However, for optical chips the cavity, the glass cap and their relevant surfaces in particular, are contributing to the overall optical performance of the device. Therefore their tolerances and quality have to meet stringent optical requirements. Fig. 2: Typical glass cavity window after dicing bonded to a dummy wafer. An 80 um glass rim acts as the bond frame with a total width of 100 um. In order to achieve these tight design rules the amount of the bond adhesive as well as its bleeding during the bonding process must be well controlled.As an example the wafer level package of miniaturized photodiodes used for high density optical storage (HD-DVDas shown in Fig. 1) is discussed, demanding special attention on advanced optical performance, UV stability and high reliability. Since intensive blue laser light (405 nm) is used, a glass window package is considered to perfectly meet the needs for long term stability and performance. Having the devices protected very early in the assembly process, ...