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The degradation behavior of the Ti/HfO x bipolar resistive random access memory (RRAM) during endurance cycles, and the operational parameters, which induce the endurance failure, are studied through the two proposed stressing methods. The over-RESET energy is considered to be the key electrical parameter to induce endurance failure in the memory device. When the device suffers the over-RESET energy, a gradually reduced memory window is observed associated with endurance cycles, and the overall degradation will include two stages. The first stage can be explained by the worn filament model and is mainly due to imbalance energy between SET and RESET process. The occurrence of unusual resistance-voltage (R-V) patterns at positive and negative voltage seep in the memory device under the second stage degradation demonstrates the existence of complementary resistive switching (CRS) in the single Ti/HfO x bipolar RRAM. After analyzing the operation conditions to activate the self-CRS in memory device with one transistor-one resistor (1T-1R) configuration, the mechanism about the second stage degradation in the RRAM originated from over-RESET energy is also discussed. A mechanism based on the worn filament model and the induction of CRS is proposed to explain the endurance failure induced by over-RESET in the Ti/HfO x RRAM with 1T-1R configuration. With an appropriate RESET energy, a robust reliability for endurance cycles is expected.

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This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (I ML-M ), 2) reduce ML parasitic load (C ML ), 3) decouple NVM-stress from wordlength (WDL) and I ML-MIS . RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128x32b RCSD nvTCAM macro was fabricated using HfO ReRAM and an 180nm CMOS. This paper presents the first ReRAM-based nvTCAM featuring the shortest (1.2ns) search delay (T SD ) among nvTCAMs with WDL≧32b.

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.