Microporous and mesoporous silicas are combined with nanoparticulate CdS particles to form hybrid photocatalysts that produce H2 from water/ethanol solutions under visible light irradiation. Catalyst structures are characterized by XRD and SEM. All hybrid materials are active photocatalysts for water splitting, and the order of photoactivity is found to be zeolite-Y > SBA-15 > zeolite-L. Silica cavity size, which determines, in part, CdS particle size, and photocatalytic activity are found to be correlated. Photocatalytic activity is seen to decrease under acidic or basic conditions with associated negative ionic strength effects. In addition, XPS analysis indicates loss of ion-exchanged and Cd2+ ion from the silicate supports occurs during the course of the photochemical reaction in solution with the complete retention of preformed and surface-bound CdS.

We have designed the first entirely asynchronous (also called self-timed or delayinsensitive) microprocessor. The design was reported at the Decennial Caltech Conference on VLSI, last March. The conference paper is included here as an appendix. Since the chips had not yet been fabricated at the moment of writing the conference paper, the paper does not include the results of the experiment.The purpose of this note is to publish these results, which are quite remarkable because of the speed reached on this first design, and, as importantly, because of the surprising robustness of the chips to variations in temperature and VDD voltage values.The processor has a 16-bit, RISC-like, instruction set. It has sixteen registers, four buses, an ALU, and two adders. Instruction and data memories are separate.The chip size is about 20,000 transistors. Two versions have been fabricated: one in 2~m MOSIS SCMOS, and one in 1.6#m MOSIS SCMOS. (On the 2/~ra version, only 12 registers were implemented in order to fit the chip on the 84-pin 6600 #m × 4600#m pad frame.)With the exception of isochronic forks (see attached paper), the chips are entirely delay-insensitive, i.e., their correct operation is independent of any assumption on delays in operators and wires except that the delays be finite. The circuits use neither clocks nor knowledge about delays.The only exception to the design method is the interface with the memories.In the absence of available memories with asynchronous interfaces, we have simulated the completion signal from the memories with an external delay. For testing purposes, the delay on the instruction memory interface is variable. 95