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A new accelerated testing scheme for detecting SRAM bit failure caused by random telegraph noise (RTN) is proposed. By repeatedly monitoring the fail bit count (FBC) under a reduced margin operation condition, increasing trend of FBC along time was clearly observed, which is believed to be caused by RTN. In addition, physics-based ultra-fast Monte Carlo RTN simulation program has been developed, which quantitatively reproduces the test results. By using the simulation calibrated by the test, product reliability against RTN can be accurately predicted.Introduction As MOSFETs are scaled down, the impact of single charge perturbation becomes more and more significant. This has led to the serious increase of random dopant fluctuation (RDF), which is urging the development of dopant-less channel FETs, such as FinFETs and ultra-thin SOI FETs [1,2]. Recently, RTN is emerging as another concern for CMOS scaling [3], which increases more rapidly than RDF by the miniaturization [4]. Though RTN is also a kind of fluctuation caused by discreteness of charges, it significantly differs from RDF in that it is time-dependent, and much fewer charges are involved. Therefore, circuit design methodology considering RTN must be newly constructed. In this paper, methods for RTN-aware SRAM design are proposed and demonstrated.Accelerated RTN Test Evaluation of RTN is usually performed focusing on individual FETs. However, due to the complexity of RTN, it is not easy to confidently predict the reliability of final products, starting solely from the characterization of individual FETs. To solve this problem, it is proposed to directly measure RTN failure events using product circuits, i.e., SRAM cell arrays. Since RTN failure is believed to be quite rare in normal operation, a method of accelerated testing is proposed. Fig.1 shows the concept of the acceleration. Note that, in present generation bulk FETs, the amplitude of random fluctuation (e.g. spread of static noise margin (SNM), etc, due to RDF and other causes) is much larger than that caused by RTN. In normal operation, where sufficiently large margin (e.g. 6σ of random fluctuation) exists, failure due to RTN occurs only when traps with large RTN amplitude accidentally reside in an SRAM cell that situates in the lower tail of the SNM distribution ( Fig.1a). Therefore, such events will hardly be detected. For the acceleration, the bias applied to the cell array is altered to intentionally reduce the margin, such that a significant portion of the SRAM bits are to fail (Fig.1b). In this situation, there are a lot of bits that are marginally operational, i.e., vulnerable to RTN switching, thus the probability of detecting bit failures due to RTN is increased.Accelerated tests were performed using 40nm generation 512kbit SRAM test chips. Cell voltages were adjusted (power supply lowered, word line voltage raised) to degrade read stability, so that about 300 to 10k bits fail at the initial reading. Then, the whole bits were read repeatedly, recording the number of fail bits along time. ...

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This paper reports the first experimental demonstration of electron mobility enhancement due to the volume inversion at relatively high N inv region (6x10 12 cm -2 ) in (110)-oriented UTB DG nMOSFETs with the t body range of less than 5 nm. The physical origin of mobility enhancement is attributable to (1) the suppression of surface roughness scattering by relaxed electric field and (2) negligibly small degradation of the mobility limited by δ tSOI -induced scattering compared to SG that severely degrades mobility in (100)-oriented UTB DG nMOSFETs by quantum confinement.