Bit-cost reduction is one of the most serious issues for file application DRAMs [l, 2, 31. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed.Multi-level storage is one circuit technology, that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory [4,5,61. When four levels are stored in a single memory cell, the effective cell size is halved.A charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4Gb DRAM.

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