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In this work, the threshold voltage (VTH) of n-channel 4H-SiC double-implanted metal-oxidesemiconductor field effect transistors (DMOSFETs) was measured after different gate-bias-stress durations to determine if the bias-stress induces a shift in the VTH. If measurement sweep time to acquire transfer curves at the conclusion of bias stress is long, the electrons may be captured by the bulk SiO2 traps or the SiC/SiO2 interface traps or emitted from these traps during the sweep, which may result in altered transfer curves and consequently an erroneous extraction of VTH. Recent measurements by Gurfinkel et al. [1], driven by the interest in faster measurement, have shown a clear dependence between the magnitude of the instability and the speed of the measurement. Hence, in this work we pursued a different approach to determine the bias-stress-induced device instability, which is to study the drain current (iDs) transient recorded during the stress. The VTH shifts and the iDS transients of n-channel 4H-SiC DMOSFETs (half cell structure as depicted in Fig. 1) were measured for different gate-bias-stress durations in the range 100 s -5500s, and at elevated temperatures. The bias stress cycle used in this work is shown in Fig. 2.Transfer curves, measured immediately after different positive-and negative-stress durations during sweep-down and sweep-up, respectively, at 30°C, are shown in Fig. 3. The VTH in this work is defined as the vGs-axis intercept of a linear fit to the 90% and the 60% values of IDS at VGS = 15 V. The VTH shift (AVTH) is calculated as the difference between the VTH extrapolated from the transfer curves taken after the positive and the negative bias-stress durations. The AVTH is plotted against the stress duration in Fig. 4. The AVTH appears to be linear with log time and is attributed to charge tunneling into the bulk SiO2 traps or SiC/oxide interface traps during the positive bias-stress, which later is emitted by the traps during the negative bias-stress [2]. The iDS transient, recorded during the positive bias-stress, appears to be linearly decreasing with log time (Fig. 5). During the bias-stress, the devices are in linear region (VDS = 0.1 V) and the linear equation of the MOSFET suggests that the AiDs is proportional to -AVTH. Therefore, a linear decrease in iDS with the bias stress time corresponds to a linear increase in VTH, which agrees with Fig. 4 results. Thus, the iDS transient technique is simpler and more accurate than the AVTH technique, to characterize the bias stress induced instability in SiC DMOSFETs. The iDS transient and the AVTH measurements were also performed at different elevated temperatures in the range 70°C -130°C (Fig. 6). Unlike as seen at 30°C, the iDS at 130°C increased with an increasing positive bias-stress time and the VTH decreased with the stress time. The iDS transient at 90°C initially shows a decay but at around 20 s starts showing an increase in iDS. This reversal in iDS and AVTH trend could be due to the presence of mobile ions in the gate oxide, which are ...

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In this work useful weight percentages of boron and phosphorus in boro-phospho-silicate-glass (BPSG) interlayer dielectric (ILD) films to getter mobile ions effectively in 4H-SiC DMOSFET structures are developed, considering the limitations, such as the required low glass flow temperature, and the possible hygroscopic nature of the films and formation of crystalline BPO 4 particles, which may occur for high B and P weight percentages. The B and P weight percentage viscous flow temperature contours and empirical inequalities representing the above-mentioned limitations are developed and discussed. Results of this work are useful for both silicon and compound semiconductor device technologies.