We report the use of inelastic electron tunneling spectroscopy (IETS) as an effective tool in studying traps in high-k gate dielectrics, particularly the electrical stress-induced traps, in metal–oxide–semiconductor (MOS) structures. Two kinds of traps may be identified by the IETS technique: (1) those that contribute to trap-assisted conduction mechanisms and (2) those that contribute to trapping in the gate dielectric. These two kinds of traps can be distinguished from each other, because each of them exhibits a distinct feature in the IETS spectra. The trap energies are readily obtained from the voltage locations where these features occur. From voltage polarity dependence of the IETS spectra, one can get information about the spatial distribution of the traps. Examples will be shown to demonstrate the capability of the IETS technique for studying traps in MOS structures with high-k gate dielectrics.

It will be demonstrated that the electron tunneling spectroscopy (ETS), obtained by taking the second derivative of the current-voltage (I–V) characteristic of a tunnel barrier, is an effective technique to probe traps in ultra-thin gate dielectrics where significant tunneling currents flow. By taking the electron tunneling spectra in both polarities, one can determine the locations and energy levels of traps that appear in the ETS spectra. The procedure for the above and the associated derivation will be presented. Examples are shown to demonstrate the use of ETS to track the evolution of traps in high-k gate dielectrics under electrical stress.

The dielectric and structural properties of LaAlO3 make it an attractive epitaxial gate oxide for nanometer-scale field effect transistors. However, the growth of epitaxial LaAlO3 directly on Si has not been possible to date. In order to achieve LaAlO3 epitaxy, we use a SrTiO3 template layer whose thickness minimizes elastic strain and atomic-level buckling at the interface. We find that LaAlO3 grown on this template layer is crystalline and initially strained, but relaxes to its bulk lattice constant within 7 unit cells. Cross-sectional transmission electron microscopy and inelastic electron tunneling spectroscopy studies of the LaAlO3/SrTiO3/Si structure show no evidence of an amorphous SiO2 layer. Capacitance-voltage measurements on thin films of epitaxial LaAlO3/SrTiO3/Si with LaAlO3 thicknesses between 13 and 110 nm show a dielectric constant for the LaAlO3 layer of 24, the same value as for the bulk. After a post-deposition low temperature anneal, these oxide heterostructures show no Fermi level pinning and an interface state density of ∼8×1010 cm−2 eV−1.

We have studied inelastic electron tunneling spectroscopy (IETS) in silicon metal-oxide-semiconductor systems with HfO2 and aluminum-doped HfO2 (HfAlO) as gate dielectrics. Samples with a thermal SiO2 layer (∼2 nm) were used to obtain reference spectra for the study. Information on chemical bonding structures and compositions of ultrathin HfO2 and HfAlO has been revealed by the IETS data. The bias polarity dependence of IETS has enabled differentiation of microstructures either near the gate electrode interface or near the silicon substrate interface.