This letter shows that the influence of the drain-source field on the potential barrier height is physically equivalent to and can be replaced by a reduction in channel doping concentration according to the formula N * ( x ) = N ( x ) -e,D(x)/q derived from the two-dimensional Poisson equation. D is found to he a simple function of channel length L and biases VDs and VBS. Thus, the actual barrier height for any drain bias and channel length can be calculated easily using well-known onedimensional (long-channel) solutions. This simple but general procedure, hereafter called the voltage-doping transformation (VDT), is shown to lead to analytically calculated potential distributions in fairly good agreement with two-dimensional numerical simulation. An application of the VDT to threshold voltage calculations also is shown. The new V,,, model is compared with measurements taken on implanted n-MOSFET's with various channel lengths. Good agreement demonstrates the accuracy of both the VDT and the new V,,, model.

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In this paper, Silicon Nanocrystals (Si-NCs) fabricated by Chemical Vapor Deposition (CVD) are, for the first time at our knowledge, successfully integrated in a 32Mb NOR Flash memory product, processed in a 130nm technology platform. The large set of data measured on arrays clearly demonstrates the robustness of our process and integration scheme. Different Si-NC deposition conditions are explored and the array voltage distribution widths are related to Si-NC size/dispersion. Main reliability characteristics, as endurance and data-retention after cycling, are studied. Results obtained on large arrays are correlated to single cell characteristics.