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This paper presents embedded DRAM device technology utilizing stacked MIM(Metal-Insulator-Metal) capacitor. Targeted for high random-access performance as well as low-power data-streaming applications, original structure named "Full Metal DRAM" has been devised and implemented from 150nm generation. This features reduced parasitic resistance of DRAM cell and fully-compatible CMOS Trs. characteristics with that of leading-edge CMOS. In 90nm generation, ZrO2 is introduced as capacitor dielectric material for cell size reduction. For the next generation of 55nm, high-k gate dielectric(HfSiON) will be introduced in CMOS platform, which can be effectively exploited for embedded DRAM scaling and performance improvement.

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We have developed embedded DRAM technology, in which 0.15pm logic transistor performance is fully compatible with that of pure logic process. The key technology is the newly developed MIM capacitor element having W/TiN/Ta,O,JTiN structure. This MIM capacitor element features that as low as 500°C is sufficient for the formation process. Excellent leakage current characteristics of 8E-15A/pm2@125"C with TJequivalent oxide thickness)=17A has been obtained. This technology has been actually implemented into 4Mbit test chip with the cell size of 0.425pm2. Over 50% yield without redundancy was obtained, confirming that there is no basic issue in process integration.