SUMMARYThe authors previously proposed an internally balanced-structure sequential circuit, being an extension of a balanced-structure sequential circuit, as a sequential circuit testable by the test generation algorithm for combinational circuits. In this paper, we propose a method of partial scan design based on such an internally balanced structure, and its test generation method. Moreover, we introduce a method of extended partial scan design, which provides transformation into easily testable sequential circuit, by replacing not only some of the flip-flops but also some wires by bypass flip-flops (that is, flip-flops offering scan and bypass functions), and propose a method of extended partial scan design that treats the kernel circuit as an internally balanced structure. Concerning this extended partial scan design, a technique is offered to select flip-flops and wires in such manner as to minimize area overhead related to scanning. Methods of test generation for kernel circuit, and methods of test generation for new circuits added in the course of scanning are examined, and test sequences generated using these methods are shown to be valid. In addition, experimental results for benchmark circuits show that the proposed partial scan design and extended partial scan design can be implemented at low area overhead. © 1998 Scripta Technica, Syst Comp Jpn, 29(10): 2635, 1998