This paper reports InAs quantum-well (QW) MOSFETs with record transconductance (g m,max = 1.73 mS/µm) and high-frequency performance (f T = 245 GHz and f max = 355 GHz) at L g = 100 nm. This record performance is achieved by using a low D it composite Al 2 O 3 /InP gate stack, optimized layer design and a high mobility InAs channel. This work is significant because it shows a possible III-V material pathway from In 1-x Ga x As to InAs with similar processing and generalized characterization, including D it .Introduction: III-V semiconductors have emerged as a promising channel material for future CMOS low power logic applications [1][2]. Their enhanced electron transport properties offer significant power reduction through aggressive supply power (V DD ) scaling. To maximize V DD scaling for logic application, both transconductance (g m,ext ) and subthreshold slope (S) must be optimized. We report 3 significant advances towards these goals: first an InAs sub channel to improve carrier transport property, second an optimized gate stack process with thin EOT of 2 nm and low D it to improve S, and third an improved layer structure with thin InP barrier (to reduce access resistance) and optimized Si δ-doping (to improve S and reduce R SD ).Experimental: Fig. 1 shows a cross-section of the device structure and Fig. 2 a corresponding TEM image of L g = 100 nm device. A thin 2 nm InP barrier was used to reduce access resistance and improve charge control, EOT and immunity to short-channel effects as well as to improve D it [3]. A 10 nm In 0.53 Ga 0.47 As/InAs/In 0.53 Ga 0.47 As composite channel with inverted Si δ-doping was chosen to improve carrier transport and electron confinement in the channel. Inverted Si δ-doping 5 nm below the channel inside the InAlAs buffer was used to supply carriers to the S/D access region and reduce R SD without adding to the barrier thickness and EOT. It is critical to carefully select the inverted Si δ-doping density to achieve the best trade-off of threshold voltage (V T ), subthreshold slope (S) and parasitic resistance (R SD ). Fig. 3 shows channel carrier density as a function of gate potential for various Si δ -doping densities. The ability to modulate the channel charge degrades as Si δ -doping increases, indicating that Si δ -doping needs to be carefully optimized for acceptable subthreshold characteristics [4]. In this work, we selected δ-doping = 1x10 12 /cm 2 , which resulted in both low R SD (enabling record high g m ) and excellent electrostatic control (enabling good S). Fig. 4 shows the corresponding conduction band profile with Si δ-doping = 1 x 10 12 /cm 2 at V GS = 0 V. In a calibration sample, we measured µ e,Hall = 11,200 cm 2 /V-sec and n s,ch = 9 x 10 11 /cm 2 at 300 K.Device fabrication was similar to that of a conventional HEMT [4], with the addition of gate oxide deposition prior to metal gate formation (3 nm of Al 2 O 3 for an EOT = 2 nm). Additionally, MOS capacitors were fabricated with a thicker 10 nm Al 2 O 3 /InGaAs to enable accurate interfacial state dens...