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SUMMARYIn this paper, we study the modem architecture for software-defined radio. We proposed a hierarchical modem architecture and a tree bus structure based on the time constraint and complexity in the signal processing in software-defined radio. We divided the functions based on the proposed architecture with the Third Generation Partnership Project Direct Sequence-Frequency Partition Duplex (3GPP DS-FDD) mode as the evaluation motive and evaluated the processing load and the flexibility. Next, we developed an evaluation board loaded with a CPU and a programmable logic device (PLD) and measured the scale of the proposed architecture and the overhead due to data transfers. On the evaluation board, the proposed architecture was implemented with 551 kGates and 5.1-Mbit circuit scale, excluding the CPU core and the transmission hardware (Tx-HW). We verified the overhead of each processor due to data transfers to be about 2.5% of the total processing load. Thus, this architecture achieved a lower frequency for the CPU operating clock and a simpler process flow, and demonstrated the ability to construct an efficient softwaredefined radio.

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