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A multi-band (bands I, II, V, VIII [option]) single-chip RFIC has been implemented in 0.18μm SiGe BiCMOS process for WCDMA/HSDPA applications. The direct-conversion receiver achieves competitive system performance: -110.5dBm sensitivity, 20dB and 12dB blocking margin for ACS case 1 and case 2, respectively, and excellent in-band blocking margins. The direct-modulation transmitter achieves more than 90dB dynamic range, and excellent EVM performance: <3.5%. In Band I, the RX section and TX section draw each 35mA and 65mA, respectively. Two dedicated on-chip fast-settling fractional-N synthesizers provide LOs for both RX and TX. The chip is housed in a 5x5 mm 2 81-pin VFBGA package.

The spectrum allocated for the operation of cellular services is country dependent and fragmented in several frequency bands [1]. Mobile phones, to be usable globally, are therefore required to support many bands. The lack of suitable tuneable pre-selection filters and duplexers mandates the use of a large number of low-noise amplifiers (LNAs) in the receiver section of the transceiver. Minimization of the area occupied by the LNAs is therefore important. Virtually every transceiver for mobile phone applications published to date makes use of LNAs employing on-chip [3,5] or on-passivation [4] spiral inductors. Spiral inductors are large and do not scale with technology, leading to an increasing relative cost of the receiver front-end with newer technology nodes. Post-passivation and SiP technologies also add noticeably to the costs. In this paper we present the first receiver employing no on-chip or above-passivation spiral inductors on the receive signal path and with a linearity and noise performance suitable for WCDMA/EDGE applications. The eight channel direct-conversion receiver is part of a multimode transceiver requiring neither RX nor TX interstage SAW filters for FDD 3G operation. A block diagram of the receiver is shown in Fig. 21.4.1.The core of the receiver is constituted by the front-end, a simplified schematic of which is shown in Fig. 21.4.2. The variable-gain LNA is based on the shuntshunt feedback topology and provides a gain of 16, 7 or -5 dB. To break the otherwise fixed relation between input impedance and the transistor transconductance, a load impedance is used, consisting of two resistors connected in series with the core of a passive mixer. The impedance looking into the mixer RF port is made very low and the node is used as a virtual ground from DC up to GHz frequencies. The resistors R LIa , R LIb , R LQa and R LQb are not only used as load for the LNA, but they are also used (i) to transform the output voltage of the LNA into an input current for the passive mixer, (ii) to isolate the I channel from the Q channel and (iii) to improve the linearity of the mixer. The last point can be appreciated by noting that most of the mixer input voltage V o LNA is dropped across the load resistors and only a very small fraction of it is dropped across the switching transistors.To more easily explain the working of the pseudo-differential variable gain LNA, Fig. 21.4.3 shows the simplified schematic of one-half of a two-gain-settings version of the amplifier. To increase power efficiency, the transconductance is implemented as a complementary stage and comprises transistors M1, M5, M4 and M10. In high-gain mode the signal current from the transconductance stage is steered by the cascodes to the output node A of the amplifier. In this mode the feedback resistor consists of the series connection of R Fa and R Fb . The load resistors R LIa , R LQa leading to the mixer core are shown for illustration purpose connected to AC ground. In low-gain mode the signal current from the transconductance stage is st...

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